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Hi there

  • Now this account is mainly for Intel internal projects use, so there will not be too many public commits. There are also some repos during my university career on this account, which have basically stopped maintenance. They should all be free to use, but cooperation projects may need to check the license;
  • If there are questions, you can contact my personal email ([email protected]), but please expect very few responses, thanks for understanding;
  • In general I am a hardware biased engineer now. Iā€™m currently working on Intel server platform development, mainly on FPGA/CPLD development, so I use Verilog/SystemVerilog heavily. I also write some C/C++/Python scripts, but mostly for my own play or use;
  • Iā€™m currently learning server platform design methodology and the code implementation of various firmware (CPLD, BIOS, BMC, etc.).

Wenxi Yang's Projects

arache icon arache

Some crawler tools in Python 3.7.

aronnax icon aronnax

SJTU Artificial Intelligence Integrated Circuit Design Contest 2019 template.

butteraugli icon butteraugli

butteraugli estimates the psychovisual difference between two images

compress icon compress

A simple image compression algorithm written in C++, and embedded implementation on Zynq.

fft_chipdesign icon fft_chipdesign

A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.

lenet icon lenet

A simple DNN for handwritten numbers recognition. Written in C++, and optimized using Vivado HLS.

platform icon platform

A simple shopping platform written in Java and HTML. Group project.

risc-v icon risc-v

A simple RISC-V CPU written in Verilog.

spiceadders icon spiceadders

A 16-bit carry skip adder and an unfinished Kogge-Stone adder.

stopwatch icon stopwatch

A stop watch which can be connected to the monitor and controlled by keyboard via VGA cable.

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