mipi_pll_div2_clk setting (using .dtsi) does update i.MX8QX clocking tree with the bogus value about linux-imx HOT 4 CLOSED

Hi Zoran,
as already explained in our customer portal to one of your colleagues (ticket 17004), there's no documentation about the possible way to change it.
According the the iMX8QX reference manual (section 8.11.3.2, table 8-17), the main PLL for MIPI DSI subsystem is 864 MHz and is not supposed to be configurable.
The name "mipi_pll_div2_clk" let me think to the main PLL divided by 2 that is actually 432 MHz as expected.
This is just how the SoC works, there's nothing to be fixed or changed.
Since we are already supporting your colleague in the customer portal, I'm now closing this issue.
BR
Pier

from linux-imx.

The name "mipi_pll_div2_clk" let me think to the main PLL
divided by 2 that is actually 432 MHz as expected.

Hello Pier,

I object and do not agree with this sentence, and the statement. Since I got 864 MHz for the mipi_pll_div2_clk. So, in the kernel run time the silicon must be able to output the correct freq, which in this case it does not.

So, we here are dealing with the bug. Since there is NO feedback between SCU unit and the main unit, my best guess.

Yes, the main PLL is fixed clock (said in the documentation, page 447), but nothing is said about mipi_pll_div2_clk in the i.MX8QX reference manual.

I think you need to provide deeper explanation about what is the connection between main PLL and mipi_pll_div2_clk, since the name is intuitive, but nothing more is said about these relations. mipi_pll_div2_clk is not even mentioned in the i.MX8QX reference manual, not even once on 9111 pages of it.

Don't you think, Pier, that this fact is a very strange fact?!

BR,
Zoran

from linux-imx.

@ZoranStojsavljevic,
IMHO, the best way to get deep details about NXP silicon is to ask NXP.
I opened a dedicated thread in NXP public forum.
Please feel free to contribute.
Thanks
BR
Pier

from linux-imx.

Hello Pier,

Actually, I found the answer on this question. To make it short (after many calculations about the maximum display resolution for MIPI DSI, and finding the correct i.MX8 Manual: i.MX 8QuadMax Applications Processor Reference Manual, Rev. 0, 9/2021), here is the essence.

The question: Given the mipi_pll_div2_clk at 432 MHz, which is the maximum display resolution for MIPI DSI ?

The answer from the i.MX 8QuadMax Applications Processor Reference Manual, Rev. 0, 9/2021 on page 5208 (chapter 15.3.2.5 DPHY PLL), it states explicitly: The VCO maximum output frequency is 800 MHz.

In other words, there is a theoretical maximum of 864 Mbit/s per data lane, which for 4 lanes gives maximum throughput of 864 Mbit/s x 4 = 3456 Mbit/s.

But, unfortunately, it is limited (by technology used) to the 800 Mbit/s x 4 = 3200 Mbit/s. The arbitrary display resolution can be used to calculate throughput.

Please, do NOT post this as answer to the NXP topic, since I would like for some time to see if anybody from NXP will take another possible explanation or route, if any???

Thank you,
Zoran

from linux-imx.