Comments (4)
So under the current single-clock semantics, such a counter is fairly straightforward, but under multiclock semantics with some notion of simulator time, it might become less clear.
For those, I was thinking:
- Probably have a way to inspect simulator time, defined in seconds
- Maybe have a way to count rising edges of clocks since the beginning of simulation, though this will need a treadle API (@chick ?) since not all clocks are necessarily under the user's control and testers2 may not be able to track everything. Note that we currently only track clocks that we know about (threads are blocked on), so rising-edges-since-beginning-of-simulation, while intuitive, might not be practical to implement. An alternative might be to have a ClockCounter / etc construct that you declare, and it tracks the number of rising edges since instantiation, but it'd be another special construct...
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Seems like the best way would be a per-clock API/object instantiated by the user...
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Yes, just per clock should do it. Something like: dut.clock().ticks()
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Continue the discussion here: about ticks under reset: start counting after reset is released. Just like you would have a hardware counter:
cnt = RegInit(0.U(32.W))
cnt := cnt + 1.U
That's what I do as workaround.
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Related Issues (20)
- JRE detects `EXCEPTION_ACCESS_VIOLATION` when trying to use Verilator as Chiseltest's backend HOT 2
- Report assert message with `FailedBoundedCheckException` HOT 1
- Generate waveform file in real-time HOT 1
- chiseltest gets the signal name wrong when trying to peek, poke, or expect an OpaqueType HOT 3
- Solver Chosen Constants for Formal Verification HOT 3
- scala.NotImplementedError: TODO: convert ThrowOnFirstErrorAnnotation HOT 3
- Bundle literal construction outside test() is not allowed in Chiseltest 5.0.0 (works in 0.5.4) HOT 2
- assertion failed: The Chisel compiler plugin is now required for compiling Chisel code HOT 1
- The waveform doesn't reflect changes in the input port until io.clock.peek HOT 1
- scala.NotImplementedError: TODO: convert DecodeTableAnnotatio HOT 7
- Will there be a chiseltest 6.0.0? HOT 16
- Frequent crash on macOS with the threaded Verilator backend HOT 6
- AXI4RAM test failed on chiseltest 5.0.2 HOT 2
- Cant ```import chiseltest._``` HOT 1
- Bitwuzla has changed it's command line argument format HOT 1
- [WARNING] Unsupported annotation: SRAMAnnotation
- [Help]A TLRAM test failed log HOT 8
- What are the future use cases of ChiselTest if it is replaced by ChiselSim? HOT 4
- Who is the copyright holder of chiseltest and what is the license? HOT 1
- one step takes extremely long time to complete HOT 2
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