Support peek/poking FIRRTL circuits/circuits with non-Chisel IOs about chiseltest HOT 5 CLOSED

This will also help a lot for re-using Chisel testers with post-synthesis/post-par netlists as well.

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I think that makes sense, though I do want to keep the chisel-level circuit interface API. So some kind of shim for a FIRRTL circuit would be needed to provide the interface definition for testers2. It could be manually written, or auto-generated.

For post-syn/post-par, testers2 already uses a name mapping table to translate the circuit interface data structures (Chisel hardware objects) to the handle needed by the underlying tester. If the IO structure is mostly the same this should also extend to post-syn/post-par, with potentially more top-level flow options needed to select what (eg particular Verilog files / simulator) to test?

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I think at the basic level just having a name mapping table from FIRRTL/Verilog to Chisel object will go a long way. The rest can be done in a modular/agile fashion.

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@azidar Treadle can peek and poke everything since it knows nothing about chisel. So would exposing the treadle api as a superset of common api (based on chisel2 and verilator simulation api) count.

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Peeking and poking firrtl circuits directly is now supported through the Simulator interface.

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