Verilog backend not work when wiring bundle from a class to another IO pin about chisel2-deprecated HOT 2 OPEN

  @Test def issue99() {

    class BigUInt extends Bundle {
      val data = UInt(INPUT, 256)
      val oflo = Bool(INPUT)
      override def cloneType() : this.type = new BigUInt().asInstanceOf[this.type]
    }

    class ModInt extends Bundle {
      val dat = new BigUInt()
      val mod = new BigUInt()
      val datOut = (new BigUInt).flip()
      val modOut = (new BigUInt).flip()
      override def cloneType() : this.type = new ModInt().asInstanceOf[this.type]
    }

    class UserMod extends Module {
      val io = new ModInt
      io.datOut := RegNext(io.dat)
      io.modOut := RegNext(io.mod)
    }

    chiselMain(Array[String]("--v",
      "--targetDir", dir.getPath.toString()),
      () => Module(new UserMod()))
  }