Comments (1)
If you have large amounts of VHDL you would like to integrate with a Chisel design, consider using the black-box functionality. In order to focus on our current backends, we do not have any near-term plans to add a VHDL backend, but there is no reason others could not make it.
We have open-sourced Chisel not only to allow the community to use it, but to also contribute to it. Feel free to fork it and implement any ideas you might have. If you think it belongs in the Chisel master branch, please submit a pull request.
from chisel2-deprecated.
Related Issues (20)
- val differs from expression after assignment
- Will OrderedDecoupledHWIOTester insert bubble for the output.ready signal? HOT 2
- OrderedDecoupledHWIOTester doesn't report error when compare failed
- Vec.fill appears to be badly broken HOT 10
- Fill(Chisel.UInt, Int) is in Chisel2, but not supported by Chisel3 HOT 1
- firrtl_interpreter/Concrete.scala: randomSInt produces out of bounds value. HOT 2
- RegUpdate and RegReset? HOT 3
- Q: "make getting-started" fails HOT 3
- Uninferrable width on reg after using fromBits
- Support bulk connects in `when`?
- Exception: sbt.TrapExitSecurityException HOT 2
- abstract type T in type pattern Chisel.Ex[T] is unchecked since it is eliminated by erasure
- Queue is not getting synthesized
- libraryDependencies latest.release not found HOT 2
- unable to create a ROM with datawidth more than 64 HOT 1
- verilator fails to compile small Example
- documentation link is dead HOT 12
- Is it legal to connect empty bundles? HOT 1
- Attaching Analog(X.W) to several Analog(1.W) HOT 1
- ccccccglcttvtcigucglvlrgbihthbuurcfiiicudnlj HOT 2
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from chisel2-deprecated.