question about Firrtl(IR) optimization about chisel-tutorial HOT 11 OPEN

While I'm not sure why FIRRTL generated _T_11, synthesis tools will almost always prune those kinds of lines so it will not consume any physical resources.

from chisel-tutorial.

But you cannot expect that synthesis tools will do these things.

from chisel-tutorial.

From our experience it usually does. Feel free to ask some others or try it yourself.

from chisel-tutorial.

@YingkunZhou it is definitely fair to say that _T_11 shouldn't be there, regardless of how it impacts final QoR. Is there firrtl output you can also post? It should be in the same directory as the verilog and have a ".fir" file extension. I think this is a backend problem more than a frontend problem, but having firrtl would be helpful in verifying that. Perhaps something is being const-prop'd and then DCE is not being run afterwards.

from chisel-tutorial.

;buildInfoPackage: chisel3, version: 3.1.5, scalaVersion: 2.11.12, sbtVersion: 1.1.1, builtAtString: 2018-12-14 23:45:23.572, builtAtMillis: 1544831123572
circuit Adder :
module Adder :
input clock : Clock
input reset : UInt<1>
output io : {flip in0 : UInt<8>, flip in1 : UInt<8>, out : UInt<8>}

node _T_11 = add(io.in0, io.in1) @[Adder.scala 17:20]
node _T_12 = tail(_T_11, 1) @[Adder.scala 17:20]
io.out <= _T_12 @[Adder.scala 17:10]

from chisel-tutorial.

not familiar with firrtl, though

from chisel-tutorial.

My output is

module Adder( // @[:[email protected]]
  input        clock, // @[:[email protected]]
  input        reset, // @[:[email protected]]
  input  [7:0] io_in0, // @[:[email protected]]
  input  [7:0] io_in1, // @[:[email protected]]
  output [7:0] io_out // @[:[email protected]]
);
  assign io_out = io_in0 + io_in1; // @[Adder.scala 17:10:[email protected]]
endmodule

Perhaps the tutorial is using an older version of firrtl?

from chisel-tutorial.

so you use master branch? I forget when and how I installed firrtl

from chisel-tutorial.

from chisel-tutorial.

from chisel-tutorial.

You may not have installed firrtl- it's included as a dependency of chisel (see here). Perhaps forcing the latest 3.1.5 for chisel will fix things? The release is a little over a week old.

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