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switchable 68K CPU-Core

VHDL 100.00%

tg68k.c's Introduction

TG68K.C

switchable 68K CPU-Core

The TG68K.C is an IP core for FPGAs. It can be easily switched between a 68000, a 68010 and a 68020. There are now many projects in the retro computer area that use this core. There was a lot of feedback from this area. So the core could develop very well. Many bugs could also be eliminated. The core does not value cycle accuracy. The core saves the FPGA resources with a good execution speed.

Der TG68K.C ist ein IP Core fuer FPGAs. Er kann auf einfache Weise zwischen einem 68000, einem 68010 und einem 68020 umgeschaltet werden. Es gibt inzwischen viele Projekte im Retrocomputer Bereich die diesen Core verwenden. Aus diesem Bereich gab es viele Rückmeldungen. So konnte der Core sehr gut weiter entwickelt werden. Ebenso konnten dadurch viele Bugs beseitigt werden. Der Core legt keinen Wert auf Zyklusgenauigkeit. Der Core schont die FPGA Resourcen bei einer guten Ausführungsgeschwindigkeit.

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tg68k.c's Issues

Address Error is missing

I'm currently trying to implement an SCC68070 which needs to run the CDi boot rom.
There is an interesting thing going wrong. The CDi boot rom forces and address error for... unknown reasons. It happens in ModelSim in my model but also in the MAME emulator. For the software this seems to be vital.

The software tries to jump to an odd location which should cause an address error immediately. This is not happening and on further notice, the trap is not implemented.

MOVEP mirroring bug

MOVEP doesn't put mirrored upper byte on the bus, when the displacement is odd.
Example (works well):

move.l #0,a1
move.l #01234567,d5
movep.l d5,0(a1)

Bug:

move.l #0,a1
move.l #01234567,d5
movep.l d5,1(a1)

Here the upper byte is preserved on every 2nd write. This causes problem on a Macintosh SE machine, where the SCSI chip is at the upper bus (15:8), and in some cases, every other byte is wrongly sent to it.

BERR support on 68010?

Hi,

Is bus error fully implemented for 68010 mode? I'm trying to implement something and don't know if the problem is with my code or the feature isn't implemented for 010.

If it's not fully done, what's missing?

Thank you for this awesome project!

Remaining issues found by the instruction tester (68020 mode)

BKPT is not implemented (not sure if it's an useful instruction):

BKPT (default):
BKPT/0000.dat (default). 0...

40850000 484b     bkpt     #3
40850002 4afc     illegal
Exception 4 stack frame mismatch:
Expected: 80.1f.40.85.00.02.00.10
Got     : 80.1f.40.85.00.00.00.10

CHK2:

CHK2.B (default):
CHK2.B/0000.dat (default). 0...

40850000 00d1 1800     chk2.b   (a1),d1
40850004 4afc     illegal
S 00000087 81.c1.2d.68.ec.60*0b.00.00.92.00.00.00.4b.6e.b6.00.02.0a.00
SR: expected 801f -> 8014 but got 801d (fff5)
.1f.40.85.00.02.00.10
Got     : 80.1f.40.85.00.00.00.10
Registers before:
D0: 000000a0 D1: 00000000 D2: ffffffff D3: 3fffffc9
D4: 87efb080 D5: 00010101 D6: 00080808 D7: 197ae7ab
A0: 00000000 A1: 00000087 A2: 00008016 A3: 00007fff
A4: 7fffff3a A5: ffffff00 A6: 4084ff00 A7: 40800400
SR:!801f      PC: 40850000 ISP: 40800800 MSP: 40800880
T1=1 T0=0 S=0 M=0 X=1 N!1 Z=1 V*1 C!1
Registers after:
SR:!801d/201d PC: 40850004 ISP: 40800800 MSP: 00000000
T1=1 T0=0 S=0 M=0 X=1 N!1 Z=1 V*0 C!1
INTREQ: c000 INTENA: c000
128 (1/2) S=0 E06=4 E09=4 E25=24 E26=8 E27=24 E28=32 E29=16 E30=16
CPUlvl=2, Mask=ffffffff Code=40850000 SP=40800400 ISP=40800880
 Low: 00000000-00007fff High: ffffffff-fffffffe
Test: 40800000-4089ffff Safe: ffffffff-fffffffe
CHK2.L (default):
CHK2.L/0000.dat (default). 0...

40850000 04d1 3800     chk2.l   (a1),d3
40850004 4afc     illegal
S 0000007f c6.00.00.dc.d6.00*00.00.81.c1.2d.68.ec.60.0b.00.00.92.00.00
SR: expected 801f -> 8019 but got 8010 (fff5)
Trace (6 stacked) SR mismatch: 8010 != 8010
Trace (6 stacked) PC mismatch: 40850004 != 40166b4c
Exception: expected 6 but got no exception.
Registers before:
D0: 0000007c D1: 00000000 D2: ffffffff D3: 3ffffb40
D4: 9fffc0a4 D5: 00010101 D6: 00080808 D7: aaaaaaaa
A0: 00000000 A1: 0000007f A2: 00007ff0 A3: 0000ffff
A4: 7fffff12 A5: 3fffffc0 A6: 4084ff00 A7: 40800400
SR:!801f      PC: 40850000 ISP: 40800800 MSP: 40800880
T1=1 T0=0 S=0 M=0 X=1 N!1 Z*1 V*1 C!1
Registers after:
SR:!8010/2010 PC: 40850004 ISP: 40800800 MSP: 00000000
T1=1 T0=0 S=0 M=0 X=1 N!0 Z*0 V*0 C!0
INTREQ: c000 INTENA: c000
96 (1/2) S=0 E04=1 E06=3 E09=4 E25=18 E26=6 E27=18 E28=24 E29=12 E30=12
CPUlvl=2, Mask=ffffffff Code=40850000 SP=40800400 ISP=40800880
 Low: 00000000-00007fff High: ffffffff-fffffffe
Test: 40800000-4089ffff Safe: ffffffff-fffffffe
CHK2.W (default):
CHK2.W/0000.dat (default). 0...

40850000 02d2 0800     chk2.w   (a2),d0
40850004 4afc     illegal
S 00007fe7 9c.94.f7.00.3c.71*32.a3.00.de.00.00.00.e2.4a.4f.00.00.00.9c
SR: expected 801f -> 8010 but got 8019 (fff5)
Trace (6 stacked) SR mismatch: 8010 != 8010
Trace (6 stacked) PC mismatch: 40850004 != 40166b4c
Exception: expected 6 but got no exception.
Registers before:
D0: 000000d6 D1: 00000000 D2: 7fffef7f D3: 3fdbffc0
D4: a1effc80 D5: 00030303 D6: 00010101 D7: aaaaaaaa
A0: 00000000 A1: 0000008b A2: 00007fe7 A3: 0000ffff
A4: ffffff4e A5: f00fffff A6: 4084ff00 A7: 40800400
SR:!801f      PC: 40850000 ISP: 40800800 MSP: 40800880
T1=1 T0=0 S=0 M=0 X=1 N!1 Z*1 V*1 C!1
Registers after:
SR:!8019/2019 PC: 40850004 ISP: 40800800 MSP: 00000000
T1=1 T0=0 S=0 M=0 X=1 N!1 Z*0 V*0 C!1
INTREQ: c000 INTENA: c000
189 (1/2) S=0 E06=4 E09=4 E25=36 E26=12 E27=36 E28=48 E29=24 E30=24
CPUlvl=2, Mask=ffffffff Code=40850000 SP=40800400 ISP=40800880
 Low: 00000000-00007fff High: ffffffff-fffffffe
Test: 40800000-4089ffff Safe: ffffffff-fffffffe

DIV:

DIVL.L (default):
DIVL.L/0000.dat (default). 0...

40850000 4c7b 1fbf 7666     divs.l   (lab_4085006a,pc,d7.w*8),d7:d1
40850006 4afc     illegal
S 4086b782 39.49.00.00.e4.00*b3.00.86.00.00.8c.13.15.c4.59.00.00.00.65
SR: expected 801f -> 8010 but got 801a (fff2)
Trace (6 stacked) SR mismatch: 8010 != 8010
Trace (6 stacked) PC mismatch: 40850004 != 40166b4c
Exception: expected 6 but got no exception.
Registers before:
D0: 000014aa D1:*00000000 D2: 7fff777e D3: 0ffff7d0
D4: 95555080 D5: 80810100 D6: 00010101 D7:*dc6f36e3
A0: 00000000 A1: 0000008c A2: 0000801e A3: 00007fff
A4: 7fffff0a A5: c03fffff A6: 4084ff00 A7: 40800400
SR:!801f      PC: 40850000 ISP: 40800800 MSP: 40800880
T1=1 T0=0 S=0 M=0 X=1 N!1 Z*1 V!1 C*1
Registers after:
D0: 000014aa D1:*763f4285 D2: 7fff777e D3: 0ffff7d0
D4: 95555080 D5: 80810100 D6: 00010101 D7:*e42e6200
SR:!801a/201a PC: 40850006 ISP: 40800800 MSP: 00000000
T1=1 T0=0 S=0 M=0 X=1 N!1 Z*0 V!1 C*0
INTREQ: c000 INTENA: c000
OK: No exception generated
3983 (1/2) S=0 E05=6 E09=6 E25=771 E26=257 E27=771 E28=1028 E29=514 E30=514
CPUlvl=2, Mask=ffffffff Code=40850000 SP=40800400 ISP=40800880
 Low: 00000000-00007fff High: ffffffff-fffffffe
Test: 40800000-4089ffff Safe: ffffffff-fffffffe
DIVS.W (default):
DIVS.W/0000.dat (default). 0...
DIVS.W/0001.dat (default). 13530...
DIVS.W/0002.dat (default). 27108...
40572 (2/2) S=0 E05=568 E09=568 E25=7713 E26=2571 E27=7713 E28=10284 E29=5142 E30=5142
All tests complete (total 40572).
CPUlvl=2, Mask=ffffffff Code=40850000 SP=40800400 ISP=40800880
 Low: 00000000-00007fff High: ffffffff-fffffffe
Test: 40800000-4089ffff Safe: ffffffff-fffffffe
DIVU.W (default):
DIVU.W/0000.dat (default). 0...

40850000 86e8 0867     divu.w   ($867,a0),d3
40850004 4afc     illegal
S 00000867 42.00.00.00.00.dd*ac.df.00.00.00.f0.3a.00.03.dc.00.00.00.00
SR: expected 801f -> 801f but got 8018 (fff2)
D3: expected ff700fdf but got bcbeffff
Registers before:
D0: 00002272 D1: 00000000 D2: eeffffff D3:!ff700fdf
D4: 90555581 D5: 80129292 D6: 02000202 D7: 26e95af7
A0: 00000000 A1: 00000071 A2: 00008002 A3: 0000ffff
A4: 7fffff5a A5: 3fffffc0 A6: 4084ff00 A7: 40800400
SR:!801f      PC: 40850000 ISP: 40800800 MSP: 40800880
T1=1 T0=0 S=0 M=0 X=1 N=1 Z!1 V!1 C!1
Registers after:
D0: 00002272 D1: 00000000 D2: eeffffff D3:!bcbeffff
SR:!8018/2018 PC: 40850004 ISP: 40800800 MSP: 00000000
T1=1 T0=0 S=0 M=0 X=1 N=1 Z!0 V!0 C!0
INTREQ: c000 INTENA: c000
OK: No exception generated
5199 (1/2) S=0 E05=80 E09=80 E25=987 E26=329 E27=987 E28=1316 E29=658 E30=658
CPUlvl=2, Mask=ffffffff Code=40850000 SP=40800400 ISP=40800880
 Low: 00000000-00007fff High: ffffffff-fffffffe
Test: 40800000-4089ffff Safe: ffffffff-fffffffe

No byte mirroring while byte write access

When CPU writes custom chipset registers in byte mode (8 bit), 16 bit data bus must be mirrored with two copies of 8 bit data.

Currently writing byte at even address leaves least significant bits in "don`t care" state, which sets custom register to unknown value.

Not compatible with 68000 mode (and possibly with 68020 either) behavior.

Thank you.

uninitialised signals in arithmetic

Hi,

Thanks for this great core

I've been using your core to validate my project in as a testbench in modelsim. I used to use the old TG68 but on upgrading to the new version I get thousands of warnings in modelsim like below [this is particularly bad in my project because the CPU is held in reset for ~250 us!]:

# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 28529424 ps  Iteration: 4  Instance: /sim_68000_tb/e_daughter/e_top/e_fb_mem

To avoid this I've added a load of initialisers (see https://github.com/dominicbeesley/blitter-vhdl-6502/blob/dev-68k/src/hdl/library/3rdparty/TG68/TG68K_ALU.vhd line 142). I'm not sure this is the right way to go about it though - I'm happy to continue doing this and make a pull request if you think it is the correct way of solving this problem

Thanks

TAS instruction not holding AS low

Hi,

It looks as if the TAS instruction is not quite correctly implemented. I think the "AS" line should stay low for between the read and write cycles but it doesn't.

Do you have any pointers on how to best fix this? I'd like to be able to test TAS properly but it's not a big deal if it is too difficult.

Thanks

Possible unintended register writes

I've been playing with the latest version of Toni Wilen's cputester, and I've noticed these:

42050000 c132 01a2 4e12 49d5     and.b    d0,([$4e12,d0.w],$49d5)
42050008 4e71     nop
4205000a 4afc     illegal
S 4206ffaa 00.49.00.00.15.00.87.00*00.00.00.cf.00.61.00.de
D 00004a0b 35.cd.29.58.00.b4.00.00*c2.00.9d.c5.00.00.cf.5e
A4: modified fffffffe -> ffffff00 but expected no modifications

42050000 02b6 93b5 94e9 21a6 5e22 43a9     andi.l   #(lab_93b594e9),([$5e22],d2.w,$43a9)
4205000c 4afc     illegal
D 00004ba8 00.00.93.53.00.82.ad.2b*00.00.00.00.00.00.84.6d
SR: expected 001f -> 0014 but got 0000
PC: expected 4205000c but got 4205001a
D3: modified ffffff00 -> ffffffaa but expected no modifications

42050000 0273 f5dd d562 f169 8de2     andi.w   #$f5dd,([-$e97,a3],-$721e)
4205000a 4e71     nop
4205000c 4afc     illegal
D 00004e2c 00.36.00.61.2e.8a.00.f5*fc.e1.00.db.d8.8b.00.fd
SR: expected 0000 -> 0008 but got 000a
A2: modified 00008000 -> 00007ffe but expected no modifications

42050000 e0f1 b7f2 0000 172c 2c71     asr.w    ([$172c],$2c71)
4205000a 4e71     nop
4205000c 4afc     illegal
S 000047a0 fb.00.5e.00.cb.50.85.63*00.ff.6f.c1.0f.00.00.00
A6: modified 4204ff00 -> 20616e64 but expected no modifications

42050000 0571 33a6 56a3 074b     bchg     d2,([$56a3],d3.w*2,$74b)
42050008 4e71     nop
4205000a 4afc     illegal
D 000005d3 54.00.25.00.e0.00.00.00*69.00.ad.4c.ed.f3.e7.34
D3: modified ffffff00 -> 00000000 but expected no modifications

...
42050000 ecf5 38cb 73a6 79d8 746d     bfclr    ([$79d8],d7.w*2,$746d){d3:$b}
4205000a 4e71     nop
4205000c 4afc     illegal
S 000029c1 00.0c.00.89.00.00.00.64*0b.00.fa.00.d2.46.00.00
D2: modified ffffffff -> 0000006d but expected no modifications

...
42050000 4cb2 0000 69e2 3d5d 72cf     movem.w  ([$3d5d],$72cf),#0
4205000a 4e71     nop
4205000c 4afc     illegal
S 000072cf 23.49.00.5d.dd.00.1e.00*00.00.ed.00.00.41.00.cd
A2: modified 42107629 -> 00000000 but expected no modifications

Absolutely crazy cases:

42050000 07b5 3f22 0f02 62a0     bclr     d3,([$f02,a5,d3.l*8],$62a0)
42050008 4e71     nop
4205000a 4afc     illegal
D 000062a4 15.a7.9f.00.91.c2.e0.00*35.00.00.29.00.00.00.6d
PC: expected 4205000a but got 4204ffee
D0: modified 00000010 -> 0000007e but expected no modifications
D1: modified 00000000 -> 0000001d but expected no modifications
D5: modified 80008080 -> 80000080 but expected no modifications
A1: modified 00000080 -> 00000086 but expected no modifications
A2: modified 00008000 -> 00008001 but expected no modifications
A5: modified ffffff00 -> ffffff04 but expected no modifications
A7: modified 42000400 -> 420003fc but expected no modifications
SR: modified 0000 -> 0018 but expected no modifications

42050000 09f7 2b62 7598 4cd5     bset     d4,([$7598,sp],$4cd5)
42050008 4e71     nop
4205000a 4afc     illegal
D 00004d36 00.4b.00.00.b9.ea.00.00*00.c7.00.a2.0b.90.f2.00
D0: modified 00000010 -> ffffffff but expected no modifications
D4: modified ffff0000 -> ffffffff but expected no modifications
D5: modified 80008080 -> ffffffff but expected no modifications
D6: modified 7fff7fff -> ffffffff but expected no modifications
A1: modified 00000080 -> ffffffff but expected no modifications
A2: modified 00008000 -> ffffffff but expected no modifications
A3: modified 00007fff -> ffffffff but expected no modifications
A6: modified 4204ff00 -> ffffffff but expected no modifications

There's more...
20200309_test.txt

Bouncing Green Cube on Hardwired demo

Bouncing green cube on Amiga hardwired demo leaves glitches.

trap/trapv stack frame error on 68010+

There's an issue with the return address saved in the stack frame for these instructions, when the long stack frame is in use:

TG68K.C/TG68KdotC_Kernel.vhd

Line 998 in b94f130

IF trap_trap='1' OR trap_trapv='1' OR exec(trap_chk)='1' OR Z_error='1' THEN

Processing the long stackframe (more than 3 words on 68010+), trap_trap or trap_trapv already reset when the PC is written, resulting saving a wrong return address (it saves the address of the TRAP instruction itself, not the next one, resulting executing the same TRAP when returning).