Comments (2)
Darn. The reset_gen became the clk_reset_gen, since the top level became a bit more complex when adding PLL and BUFG. I need to add a verilator specific reset_gen.
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Fixed the issue by adding a separate reset generator in the tb directory. I also changed names on Verilog source files groups in the Makefile to make it more distinct that there are some source files specific to building the FPGA, some source files that are specific for the Verilator simulation, and some source files that are common to both targets.
See b2ca3f2?diff=unified for the commit details.
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Related Issues (20)
- Add a Verilog formatter
- Make testbenches self testing, and with correct exit code
- Idea: ability (but not enforced) to clear (or R/W) CDI HOT 4
- Improve community information about the project HOT 1
- Increase clock frequency of application_fpga HOT 2
- Clean up UDI and UDS implementation as well as udi_uds_patch program
- Add support for client based device reset HOT 14
- support for OpenPGP? HOT 1
- Rewrite code to reduce resource allocation HOT 1
- Update core local Makefiles to use Verilog-2005 for sim, linting
- Hardware support to access flash from CPU
- Signal to firmware not to load app from flash HOT 2
- FW: Optionally start app from flash
- CH552 fw: Support for different USB classes: CDC and HID
- Support communication to different USB endpoints
- FIDO2 device app
- Change names of ADDR_RAM_ASLR and ADDR_RAM_SCRAMBLE HOT 1
- Device app to test hold touch HOT 1
- Remove possible redundant RAM clearing functionality HOT 1
- Remove possibly redundant randomized RAM scrambling during randomised RAM fill
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