Comments (3)
Hi Marcelo,
This repository contains a wrapper for using the alt_jtag_atlantic
module in Bluespec. If you use Bluespec, the wrapper exposes two FIFOs (rxfifo and txfifo) where you can get/put bytes. It is really easy to use, just see the examples.
If you use Verilog or VHDL, you can instantiate alt_jtag_atlantic
directly. Its signals are:
r_ena
(output): tells if you can write a byte to the UART during the next cycle (important: it's not during the current cycle! it's during the next one).r_dat
andr_val
(inputs): provide a byte tor_dat
and assertr_val
high to write the byte to the UART.t_dav
(input): assert high if you want to read a byte from the UART during the next cycle.t_dat
andt_ena
(outputs): ift_ena
is high, then a byte is ready to be read fromt_dat
.
Please note alt_jtag_atlantic
is not a part of this project. It is a "builtin" module of Altera's synthesizer. If you are using Verilog or VHDL you don't need anything from this project (for the hardware part), only the documentation above.
As for the software part, you can refer to the software
directory.
Please feel free to reopen this issue if you need any further information.
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FYI this may be a helpful example: https://github.com/tommythorn/yarvi/blob/master/shared/axi_jtaguart.v
from alterajtaguart.
from alterajtaguart.
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