In the neo430 Xmen .vhd , we knows 1x16bit splite to 2x8bit , but why the WEbit is 2bit ?
I see the RTL, Xmem's R/W_ADDR was connect to addr_i [9:1] , I donot understand it .....
RTL/ Xmem.vhd :
acc_en <= '1' when (addr_i >= imem_base_c) and (addr_i < std_ulogic_vector(unsigned(imem_base_c) + IMEM_SIZE)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(IMEM_SIZE/2) downto 1))); -- word aligned
i want to use 2pcs 8bit eeprom and 2pcs 8bit sram replace the imem and dmem ,
when i use 2x8bit memory , i splite the data[15:0] to data[15:8] and data[7:0] , only 1 WEbit , can it works ?
i found the ice40up Xmem.vhd :
spram_we <= '1' when ((acc_en and (wren_i(0) or wren_i(1))) = '1') else '0'; -- global write enable
spram_be(1 downto 0) <= "11" when (wren_i(0) = '1') else "00"; -- low byte write enable
spram_be(3 downto 2) <= "11" when (wren_i(1) = '1') else "00"; -- high byte write enable
does it means every clk only to do 1 mission : only read / write low byte / write high byte / write a word ?
so ........for mychip( clk, addr, dout, din , we ) ---> it need to writing like these ?
mymem_clk <= std_logic(clk_i);
mymem_addr <= std_logic_vector(addr_i(13+1 downto 0+1)); -- addr /2
mymem_din <= std_logic_vector(data_i(15 downto 0));
rdata <= std_ulogic_vector(mymem_dout );
mymem_we_low <=std_logic( wren_i(0) );
mymem_we_high <=std_logic( wren_i(0) );
acc_en is not need now ?
how about the 16bit flash and 16bit sdram interface ?
mymem_clk <= std_logic(clk_i);
mymem_addr <= std_logic_vector(addr_i(13+1 downto 0+1)); -- addr /2
mymem_din <= std_logic_vector(data_i(15 downto 0));
rdata <= std_ulogic_vector(mymem_dout );
mymem_we <=std_logic( wren_i(0) or wren_i(1) );
sorry for my VHDL , i just learn it yesterday ........