Comments (4)
This looks like a much bigger headache than I thought it would be. I'll try to get to this soon, depending on deep it goes. Eech.
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Do you know exactly what we want to do here? Is it mostly "just" merging Rb and Rl into the same thing?
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Yeah. That's the idea. Make Rl look like the 8-bit version of R16.
It's a huge refactoring, though, so I'm staying away from it for now. I'm
just leaving this here as a reminder to do it eventually.
On Sun, Nov 9, 2014 at 5:54 PM, Berkeley Churchill <[email protected]
wrote:
Do you know exactly what we want to do here? Is it mostly "just" merging
Rb and Rl into the same thing?—
Reply to this email directly or view it on GitHub
#40 (comment).
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Also just noted, the way codegen works, we don't generate instruction variants of the form:
OP RB, RH
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Related Issues (20)
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- need more xor opcodes in is_xor_reg_reg()
- regression in #223
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- Examples need updates? HOT 1
- push/pop not assembled correctly
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- Parser parses all memory dereferences as 8-bit HOT 4
- Latency table wrong/out-of-date HOT 1
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- Need way to get function buffer from assembler HOT 1
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