Comments (2)
I've implemented extraFlags for verilator:
#140
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Thanks for the fix
from spinalhdl.
Related Issues (20)
- WishboneSlaveFactory - doWrite is never called in pipelined mode HOT 3
- Wishbone BusIf SEL usage HOT 1
- Formal verifiation: SymbiYosys of SpinalTemplateSbt fails with "RG_WIDTH > 1 is not support by async2sync, use clk2fflogic." when using async reset
- Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys HOT 10
- Set clock domain from blackbox HOT 2
- Error when create a new ClockDomain in simulation HOT 2
- SystemVerilog Interface Support HOT 2
- NamedType returns null when called outside of a Component HOT 11
- AxiLite4SlaveFactory generates combinatorial paths from inputs to ready outputs HOT 5
- Signal naming oversights HOT 3
- `onSamplings` error when use inside clockdomain
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- Plugin deadlock in circular dependency on Handle HOT 5
- SpinalSim: onSamplings can't work properly with clock from a blackbox HOT 8
- When to override `clone`? HOT 7
- How to use Union in IO port HOT 1
- `assignDontCare` on Bundle element inside Union does not work HOT 14
- StateMachines inside Plugins that have multiple instances have naming clash HOT 2
- `Union` elements cannot be accessed inside SpinalSim properly HOT 1
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from spinalhdl.