RegIf AxiLite4 Problem:Data should be avaliable when Valid and Ready is active about spinalhdl HOT 11 CLOSED

class regAxiLite extends Component {
    val io = new Bundle {
        val axiLite = slave(AxiLite4(32, 32))
    }
    val busIf   = AxiLite4BusInterface(io.axiLite, (0x000, 48 Bytes), "Test_axilite")
    val test0   = busIf.newReg("Test_reg")
    val test0_0 = test0.field(Bool(), RW, 1)
    val test0_1 = test0.field(Bool(), RW, 0)
    val test0_2 = test0.field(Bool(), RW, 1)
    val test0_3 = test0.field(Bits(3 bit), RW, 7)
    val test0_4 = test0.fieldAt(pos = 8, UInt(8 bit), RW, 2)
    busIf.accept(RalfGenerator("header"))
}

object regAxiLiteSim extends App {
    Config.sim.compile(new regAxiLite).doSim { dut =>
        // Fork a process to generate the reset and the clock on the dut
        dut.clockDomain.forkStimulus(period = 10)
        SimTimeout(100000)
        val port = dut.io.axiLite

        port.aw.valid #= false
        port.w.valid #= false
        port.ar.valid #= false
        port.r.ready #= false
        port.b.ready #= false

        sleep(1000)
        dut.clockDomain.waitActiveEdge()
        port.ar.valid #= true
        port.ar.addr #= 0
        port.ar.prot #= 0
        dut.clockDomain.waitActiveEdge()
        while (!port.ar.ready.toBoolean) {
            dut.clockDomain.waitActiveEdge()
            println("Wait for ar ready active...")
        }
        port.ar.valid #= false
        dut.clockDomain.waitActiveEdge()
        while (!port.r.valid.toBoolean) {
            dut.clockDomain.waitActiveEdge()
            println("Wait for r valid active...")
        }
        //Wait for a extra clk, it's in line with the rules, right?
        println("Wait for a extra clk...")
        dut.clockDomain.waitActiveEdge()
        port.r.ready #= true
        println("Data is " + port.r.data.toBigInt.toString())
        dut.clockDomain.waitActiveEdge()
        port.r.ready #= false
        sleep(1000)

    }
}

  private def readGenerator() = {
    when(askRead){
        readData  :=  .....    //readData hold
    }.otherwise{
      readError := False
    }
  }
}

  private def readGenerator() = {
    when(askRead){
        readData  :=  ..... 
    }.otherwise{
      readData  := readDefaultValue  //rdata cannot be retained, otherwise there will be security risks , SO KEEP 0 or defualtValue
      readError := False
    }
  }
}