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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

catapult

Deprecated Catapult GitHub. Please instead use http://crbug.com "Speed>Benchmarks" component for bugs and https://chromium.googlesource.com/catapult for downloading and editing source code..

fflib2

fsclalgorithmtesting

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

portals4

Portals is a low-level network API for high-performance networking on high-performance computing systems developed by Sandia National Laboratories, Intel Corporation, and the University of New Mexico. The Portals 4 Reference Implementation is a complete implementation of Portals 4, with transport over InfiniBand VERBS and UDP. Shared memory transport is available as an optimization, including Linux KNEM support. The Portals 4 reference implementation is supported on both modern 64 bit Linux and 64 bit Mac OS X. The reference implementation has been developed by Sandia National Laboratories, Intel Corporation, and System Fabric Works. For more information on the Portals 4 standard, please see the Portals 4 page.

pspin-snitch

pulp-riscv-binutils-gdb

pulp-riscv-gcc

pulp-riscv-gnu-toolchain

snitch

Lean but mean RISC-V system!

snitch_tracer

sst-elements

SST Architectural Simulation Components and Libraries

trace2source

VSCode extension to relate PULP core traces to source files.

tracevis