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jim-wilson avatar jim-wilson commented on August 30, 2024

It was removed same time the RISC-V support was upstreamed to FSF GLIBC. I think it was removed because we couldn't prove that it worked. SiFive is the only company working upstream, and we only make rv64gc linux hardware, so that is the only thing we can test on hardware. We can test others on qemu, but it takes longer, and we had a deadline to hit to get the patches in, and limited number of people to do the work, so some things had to be sacrificed. One of those was rv32 support that was added later by WDC, based on patches originally written at Andes. Looks like one of the others was the single float support. If anyone ever volunteers to do RISC-V GLIBC work it could be readded, but I've been waiting 3 years for someone to take up GLIBC support and it hasn't hanppened yet.

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higuoxing avatar higuoxing commented on August 30, 2024

Hi @jim-wilson, thanks a lot! I'm interested in re-adding it to RV GLIBC. I will give it a try in my spare time.

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jim-wilson avatar jim-wilson commented on August 30, 2024

If you want to contribute to an FSF project, you need a personal copyright assignment and a disclaimer from your employer, or alternatively a corporate copyright assignment from your employer. These can take some time to get, and depending on who you work for might be difficult to get, so if you do decide to write glibc patches, you should look into this before you finish the patches. You can start the process by sending email to [email protected] and they will ask what program you are working on and who you work for, etc. Looks like you might be a college student, so the same rule applies if the university you attend can claim your work.

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jim-wilson avatar jim-wilson commented on August 30, 2024

I already answered this.

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