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Comments (4)

palmer-dabbelt avatar palmer-dabbelt commented on August 29, 2024 1

The CSR instructions take indicies as arguments in addition to names, so you can work around this without a toolchain change.

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michaeljclark avatar michaeljclark commented on August 29, 2024

I think something like the following needs to be added to riscv-binutils-gdb/include/opcode/riscv-opc.h. I will try locally.

#define CSR_HEDELEG 0x202
#define CSR_HIDELEG 0x203
#define CSR_SEDELEG 0x102
#define CSR_SIDELEG 0x103
DECLARE_CSR(hedeleg, CSR_HEDELEG)
DECLARE_CSR(hideleg, CSR_HIDELEG)
DECLARE_CSR(sedeleg, CSR_SEDELEG)
DECLARE_CSR(sideleg, CSR_SIDELEG)

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palmer-dabbelt avatar palmer-dabbelt commented on August 29, 2024

@aswaterman Are this going into the next supervisor spec, or should I close this bug? I see only medeleg/mideleg in parse-opcodes.

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aswaterman avatar aswaterman commented on August 29, 2024

Let's close this for now. We are punting both the hypervisor mode and user-level interrupts to the version after next, so neither set of registers will be in the coming version.

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