Related Issues (20)
- backdoor read has no side effect HOT 1
- Specify reset domain
- [VHDL] Array port
- [Request] Add support for library name HOT 15
- [VHDL] Type mismatch error for an array register with offset address 0x0 HOT 1
- rc, w0c, w1c, wc, woc: bit field set when it should be cleared? HOT 3
- Veryl support
- Parameterized bit field with
- Support Pkl format HOT 1
- PyUVM support
- Allow to specify runtime options by using config file
- [bug] external register type seems to not be working HOT 4
- DSim cannot compile generated VHDL HOT 2
- XLSX input error description row/column off by one HOT 1
- [Bug] NoMethodError is raised when loading XLSX spreadsheet HOT 1
- rggen-vhdl generates APB interface when the protocol is specified as wishbone HOT 15
- Setting protocol in the register map file has not effect and there is no warning/error HOT 1
- Add variable placeholders for comments HOT 6
- Report error when unknown field is given
- Allow to specify configuration parameters on register map files
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