ranjan-yadav Goto Github PK

analog-digital-communication

Contains general codes related to ADC

automatic-street-light

It contains the pdf of the group project that i performed. The idea is if there is no traffic all lights should turn off and also based on number of traffic street light must glow. It also pre-informs the passengers on road via dispay board the ammount of traffic on subsequent road and thus passenger may turn their path to avoid any traffic. It also had a customized app for Accident through which driver may send his location and other information based to concerning authorities.

blynk-app-nodemcu-and-other-sensors

cigs-based-multi-junction-solar-cell-enhancing-efficiency-by-inserting-sns-layer

To enhance the efficiency of earlier presented, CIGS based 3-layer MJ solar cell by inserting the novel back surface field (SnS) layer. Also, to analyze the effects of changing the width parameter for absorber, buffer and back surface field layer and to implement ZnS as buffer layer and establishing it as substitute for CdS.

farmer-s-friend

“Farmer’s Friend” is an autonomous ground vehicle (rover) designed to increase the quality and yield of crops (we are focusing mainly on Tomatoes). It is amalgamation of software and hardware which will be used by the customers mainly farmers to detect pest attacks in their farms that will work on it’s own without any human intervention. We are using image processing techniques to differentiate between healthy and defective crops.

fpga_140_pin

Developed a FPGA board PCB layout consist of core FPGA IC , ADC, DAC ,ENCODERS, VGA PINS, KEYPAD etc. using orcad software (Group Project).

high-efficient-cigs-based-solar-cell

To simulate the high efficiency CIGS(Cu(In,Ga)Se2) based Solar Cell using SCAPs 1D tool and analyze the influence of buffer layer on the CIGS-based Solar cell. Also PV parameters are calculated for different buffer layer (CdS,ZnS,ZnSe) and find the alternative of CdS.

i2c-protocol

iot-based-industrial-automation

It consist of all the idea along with codes, ppt, report, video. The basic idea was to control the conveyer belt using IOT from distant using app and based upon correct dimension and everything it has to accept or discard the object on belt.

neural-amplifier-with-capacitive-feedback

power-point-presentation

Consist of PPT

print-name-using-verilog

This code provide you accessibility to type statements/name/word into the waveform using Verilog. Used basic State machine. Refer Test Bench for how to give input pattern. I have used ISE design Suite by xilinx as tool

sha-256-system-verilog-code

The complete code for SHA-256 has been implemented on questasim using system verilog and output has been for 256-random input given by user. For verification with real output , I have used an online website link as follows: https://www.movable-type.co.uk/scripts/sha256.html , which generates the SHA-256 output for a message.

spi-protocol

tmds-encoder-8b-10b

TMDS is a method for serially transmitting high-speed digital signals. The “transition minimized” part is realized by the 8b/10b encoding algorithm used by TMDS, which is implemented here in digital logic. This TMDS encoding is used in several digital communication interfaces, including the DVI and HDMI video interfaces. It is important to note that this TMDS encoding was created by Silicon Image in 1999 and is not the same as the original 8b/10b encoding introduced by IBM in 1983. The “differential signaling” part of the technique relates to the IO circuit and is not discussed in detail here. The TMDS encoding algorithm reduces electromagnetic emissions, achieves DC balance on the wires, and still allows for reliable clock recovery. The encoding seeks to minimize the transitions (thus reducing interference between channels) while still retaining frequent enough transitions for clock recovery. By keeping the number of ones and zeros on the line nearly equal, the DC balance part of the encoding algorithm improves the noise margin.

universal-ansynchronous-reciever-transmitter

32-bit UART with start and stop bit.

verilog-codes

BASIC VERILOG CODING (with test bench files { **_tb.v files})