Comments (4)
you want them?
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Where are the .py files mentioned in the readme.me?
i have uploaded 2 of the files. the 3rd one, I am rewriting, because i am not happy with the first way i wrote it
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Sure thanks either way. I was curious to see what they were.
💡 I'll see your script and raise you one!
Here is one I wrote to convert Telescan PE .tlscan to .coe files.
Feel free to add it to your repo if you like.
It groups the DWORDs the same way as "pcileech_cfgspace.coe", but I was thinking of of breaking them down in smaller DWORD groups to make it easier to manually edit. I pretty much gave up on doing customizations this way. I think it will eventually take making the pcicleech gateware to not use the Vivado PCIe IP. And replace it with a custom/open-source one that completely ignores the config space (other than BAR setting which might be a requirement). Then one could put anything for a config space and have it not matter (probably).
from dma.
Sure thanks either way. I was curious to see what they were.
💡 I'll see your script and raise you one!
Here is one I wrote to convert Telescan PE .tlscan to .coe files.
Feel free to add it to your repo if you like.
It groups the DWORDs the same way as "pcileech_cfgspace.coe", but I was thinking of of breaking them down in smaller DWORD groups to make it easier to manually edit. I pretty much gave up on doing customizations this way. I think it will eventually take making the pcicleech gateware to not use the Vivado PCIe IP. And replace it with a custom/open-source one that completely ignores the config space (other than BAR setting which might be a requirement). Then one could put anything for a config space and have it not matter (probably).
Good stuff man. I'll definitely have a look at this when I have the time ❤️
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