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adv_dbg_if

Advanced Debug Interface

apb2apbcomp

Conversion between the PULP apb and the compliant one

apb2per

apb_adv_timer

Advanced timer with APB interface

apb_fll_if

Control interface for FLL

apb_gpio

apb_interrupt_cntrl

Small and simple APB interrupt controller

apb_node

arnold-sdk

Repo to support evaluations using Salinas board

axi

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

axi_node

AXI X-Bar

axi_slice

Pipelines the AXI path with FIFOs

axi_slice_dc

AXI Dual-Clock FIFO for clock domain crossings (CDC)

common_cells

Common SV components

common_verification

SystemVerilog modules and classes commonly used for verification

conda-eda

Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

core-v-mcu-eclipse

eclipse project that uses FreeRTOS kernel and runs on core-v-mcu

core-v-mcu-old

This is the top-level project for the core-v-mcu project, which updates the core-v-mcu to use the released cv32e40p core and adds eFPGA

core-v-mcu-sdk

Eclipse+FreeRTOS SDK for core-v-mcu

core-v-mcu-soc

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

edalize

An abstraction library for interfacing EDA tools

eos-s3

Device description files (architecture, timing, configuration bitstream, and general documentation) for EOS S3 MCU+eFPGA SoC

eos-s3-hal

foedag

Open EDA GUI

fpga

fpga-tool-perf

Repo for checking the tool permance

fpga-tool-perf-public

FPGA tool performance profiling