Related Issues (20)
- missing assertions.svh in common_cells.core HOT 1
- A gated shift register module HOT 2
- Clock divider configuration fails if divider value is 0
- feature/idea: using a multiplexer to iterate between new and old values in clk_int_div
- Recent change in verilator broke stuff (or at least that's my understanding of it)
- a bug in lzc module?
- popcount for INPUT_WIDTH=1
- Width mismatch error in assign statement with VCS strict compile
- spill_register_flushable assertion improvement HOT 1
- No assertions in Verilator
- Remove wrappers
- Remove deprecated IPs
- Documentation Needed for "stream_xbar.sv" HOT 1
- Found a bug in "stream_xbar" module when two different "sel_i" have same value HOT 4
- Need clarification of assertions failure in stream_xbar module HOT 7
- In stream_xbar module, when flush_i is asserted, ready_o[31] remains unset (not set to 0). HOT 7
- Round robin arbitration is not properly implemented in stream_xbar.sv module HOT 5
- ‘steam_join_dynamic’ handshakes unselected streams
- question about CDC modules for synchronization flops
- `stream_arbiter` with priority arbitration inherently violates assertion
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from common_cells.