Comments (1)
Hi @hossein1387, thanks for your questions.
- I was wondering which axi interface do you recommend?
For reading and writing a few control registers, AXI4-Lite should do. It should be fairly straightforward to write a module that translates the memory "protocol" of your processor's LSU to AXI4-Lite.
- Also, what are the minimum pulp blocks I need to use?
This repository currently depends on v1.21.0
of pulp-platform/common_cells
. There are no other dependencies for using the AXI modules.
- Finally I am planning to implement my system on a Xilinx FPGA and since I might move toward ASIC implementation, do you recommend to use Xilinx IPs for FPGA and your IPs for ASIC or can I use your IPS for both scenario?
I would use the same IPs on the FPGA and the ASIC, simply because it reduces the differences between ASIC and FPGA. The more of your hardware is exactly the same (at least in terms of RTL code) on FPGA and ASIC, the more you can verify and prototype on the FPGA before tapeout, and the higher confidence you can have that your RTL does not have major flaws.
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Related Issues (20)
- `axi_to_mem_banked` demux hardware overhead
- `axi_burst_splitter` inverse functionality for Modifiable bit HOT 1
- axi_sim_mem write after read leads to AXI error HOT 1
- axi.core needs dependency for common_verification
- Should we add an option to force aligned accesses of given `ax_size` in class `axi_rand_master`? HOT 1
- Example of usage for axi_to_axi_lite converter
- Improve AXI cut/multicut.
- [Question] AXI Ordering
- `axi_to_mem`: Comb path from `b_ready` to `w_ready` HOT 1
- axi_to_mem: Starvation issue: AW channel blocks AR channel forever
- axi_dw_downsizer: AXI Slave BRESP changes in value during BVALID’s wait for BREADY
- axi_pkg::LenWidth not compatible with vivado IP packager
- axi_cdc fpga implementation very inefficient HOT 2
- run_vsim.sh: Run simulations in parallel HOT 4
- tb_axi_lite_xbar is not included in scripts/run_vsim.sh
- Vivado Synthesis Error - [Synth 8-6038] cannot resolve hierarchical name
- ``axi_to_mem``: Error response signals in B and R response channels
- axi_dw_downsizer writing data beats with wstrb == 0
- Logging not supported for Queue item error : AXI HOT 2
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