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cxd4 avatar cxd4 commented on June 28, 2024

There is a benefit to the ordering of the instructions.

On a CPU of Intel's nature, you can typically achieve higher performance beyond simply measuring the cycles or independent latency of each operation compiled--often times you can get a better throughput by ordering instructions of alternating units and types (like on the RSP, how you can execute 2 instructions in one cycle if scalar opcodes are interleaved with vector ones).

But Azimer and Jabo would know more about it.

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LegendOfDragoon avatar LegendOfDragoon commented on June 28, 2024

Makes sense. I sorta forgot about the fact that Jabo implemented some HLE code, so there is a point to using it.

I just felt that without HLE code or register caching, it wasn't worth the effort, since it just makes the recompiler even more error prone. I didn't pay enough attention to Jabo's HLE code, so I'll have to go analyze that and figure out what went wrong.

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LegendOfDragoon avatar LegendOfDragoon commented on June 28, 2024

Looks like zilmar fixed it :) . Tested SD Hiryuu and is no longer bugged with instruction reordering enabled.

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project64 avatar project64 commented on June 28, 2024

Yoshi's Story as well ?

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LegendOfDragoon avatar LegendOfDragoon commented on June 28, 2024

Oh my bad, I think the problem with Yoshi's Story was something else. Either way, the graphical issues I saw in the original RSP 1.7.0.9 are gone now, for Yoshi's Story.

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