Comments (3)
bugadani
commented on June 9, 2024
What does unlocking mean in this context? We support architectures that don't understand this term.
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Yatekii
commented on June 9, 2024
Well, whatever it means within the arch. unlocking/enabling is used interchangeably. We will have to work out the exact API/requirements.
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bugadani
commented on June 9, 2024
An interesting question: can we define halting and resuming (also, system reset [and halt]) in a multi-core system (both the expected semantics, as well as per-system properties)? Currently we print warnings if we find that a core's state is not as we expect, but that isn't an error if halting one core halt every core.
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Related Issues (20)
- Make the debugger a separate project that can debug x86
- Stable scripting API in the CLI
- Xtensa: `wait_for_core_halted` sets INTLEVEL to 1
- [feature request] Add pre-verify before flashing
- Fail to compile via cargo `error: failed to run custom build command for libudev-sys v0.1.4` HOT 2
- Typo in Stlink `swj_sequence` function
- STM32H745IIx RTT does not work unless both cores are running. HOT 2
- Unable to flash STM32F303VCT6 discovery board: Timeout while erasing flash sector HOT 2
- AVR support
- Insufficient DWARF info with recent nightly HOT 5
- More advice if device not found (error messages) HOT 4
- Raspberry Pi Pico + pico-debug: device already open HOT 2
- A <lvl> prefix started appearing between 0.22.0 and 0.24.0 HOT 2
- `cargo install probe-rs-tools` warns about yanked `zip` dependency HOT 2
- v0.24: Flashing is broken with j-link on AT32F437VMT7
- Prerequisites are not correct HOT 8
- Got "Unexpected semihosting command" when running embedded-test on NUCLEO-H743ZI
- HIL tests fail on H2 with probe-rs 0.24.0 HOT 2
- CMSIS-DAP and bitbanging ARM interface differs in error handling
- Double-check STM memory ranges HOT 1
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