Issues with Logic 8 about python-saleae HOT 2 CLOSED

Hmm.. I'm not sure about this. @Marcus10110 is there an expected behavior here?

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There is nothing in the software to guarantee that the sample rates are sorted, but in general, I would expect them to be sorted from analog slowest to analog fastest. (this implies digital fastest to digital slowest, but due to complex FPGA requirements, you will find frequent exceptions to this)
It's possible that analog sample rates are always sorted from fastest to slowest.

Basically, for any given performance setting (which directly relates to USB throughput) the available sample rates try to offer a trade off between digital and analog sample rates. (i.e. trade analog bandwidth for digital bandwidth, and vice versa)

I would update set_sample_rate_by_minimum to scan all performance options, and every sample rate option. I would ignore sorting and check every option, while tracking the lowest analog & digital pair that satisfies the requirement.

if you would like to select exactly the slowest sample rate for a given requirement, the USB bit rate can be calculated like this:

ADC width = 12 bits for Logic 8, Pro 8 and Pro 16.
ADC width = 8 bits for logic 4.

Bandwidth (bits per second) = (digital_sample_rate * digital_channel_count) + (analog_sample_rate * analog_channel_count * adc_width).

That's the exact USB bandwidth requirement for any sample rate combination. There is no additional overhead. The lower the bandwidth, the higher the reliability for long duration captures. (this really only affects the original Logic and Logic 4, and only on poor-performance host controllers)

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