Comments (1)
This is expected behavior, and is a limitation of the FTDI chips themselves.
As with many pieces of hardware that accept a programmable clock rate, the FTDI
chips accept not an absolute clock rate, but rather a divisor that is used to
derive the desired clock rate from the primary clock. These divisors are
finitely precise; in the case of the FTDI chips, the divisor is a 16 bit value.
So you can't set the clock rate so something as specific as 15.000001MHZ.
If you take a look at the freq2div code in the support.c file, you'll see the
algorithm used to derive a divisor from a given clock frequency, as specified
in the FTDI data sheet (not complicated). Basically, any value above 15MHz will
result in a divisor of 0, which gives you a clock rate of 30MHz. Any value
between 10 and 15MHz gives you a 15MHz clock rate and a value between 6 and
10MHz gives you a 10MHz clock rate. Values from 1-6MHz can be specified
exactly, in 1MHz steps.
Original comment by [email protected]
on 25 Jul 2012 at 7:29
- Changed state: Invalid
from libmpsse.
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from libmpsse.