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abc

ABC: System for Sequential Logic Synthesis and Formal Verification

abc_py

accelerated_cpp

am

amg

approximate-multiplier

This repository contains approximate 8-bit multiplier Verilog code.

approximate-multiplier-on-gaussianblur

asap7

bib-abbreviation

This is a lightweight python script to abbreviate the journal names in your latex bib file.

blogs

cirkit_py

common_cells

Common SystemVerilog components

dagp

Multilevel Directed Acyclic Graph Partitioner

daily_fudan_actions

daily_fudan的运行器，自动定时执行https://github.com/Limour-dev/daily_fudan_core 的代码。请按daily_fudan_core的readme正确配置FUDAN，按本仓库的readme正确配置GH_PAT。两个secrets都在本仓库配置，注意不要配置到core仓库。

daily_fudan_core

daily_fudan的代码，无需fork；请fork https://github.com/Limour-dev/daily_fudan_actions 来自动执行该repo下的最新代码。有问题请提issue

drills

DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

drum

The Verilog source code for DRUM approximate multiplier.

espresso-logic

A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.

fpga-based_approx_mult

FPT'22 Artifact_ Evaluation

google-translate-for-goldendict

Add Google translate to GoldenDict

hdl-benchmarks

Collection of open HDL modules, subsystems and microprocessors (benchmarks) that are used for related tools testing.

hebo

Bayesian optimisation library developped by Huawei Noah's Ark Lab

ic

lsoracle

metis

opdb

OpenPiton Design Benchmark

rl_logic_synthesis

simon_speck_ciphers_c_algorithm

A project mostly with Simon Cipher C code.

simon_verilog

Simon Cipher verilog/system verilog code.

yosys

Yosys Open SYnthesis Suite