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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

bender

A dependency management tool for hardware projects.

chat-builder

common_cells

Common SystemVerilog components

common_verification

SystemVerilog modules and classes commonly used for verification

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

flexproxy

flexlm proxy

floonoc

A Fast, Low-Overhead On-chip Network

hbm-utils

HBM package and symbol generation scripts

hero

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

idma

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

iree

A retargetable MLIR-based machine learning compiler and runtime toolkit.

kipart

Python package for generating multi-unit schematic symbols for KiCad from a CSV file.

llama

Inference code for LLaMA models

llama2.c

Inference Llama 2 in one file of pure C

llm-viewer

Analyze the inference of Large Language Models (LLMs). Analyze aspects like computation, storage, transmission, and hardware roofline model in a user-friendly interface.

mlir-llm-runner

occamy

A high-efficiency system-on-chip for floating-point compute workloads.

register_interface

Generic Register Interface (contains various adapters)

riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

shark-turbine

Unified compiler/runtime for interfacing with PyTorch Dynamo.

snitch-public

Lean but mean RISC-V system!

snitch_cluster

An energy-efficient RISC-V floating-point compute cluster.

tech_cells_generic

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

tinytrainer

Using huggingface transformers library to create tiny language models