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aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

deeplearning

Python for《Deep Learning》，该书为《深度学习》(花书) 数学推导、原理剖析与源码级别代码实现

dive-into-dl-pytorch

本项目将《动手学深度学习》(Dive into Deep Learning)原书中的MXNet实现改为PyTorch实现。

dma-proxy-native

e200_opensource

The Ultra-Low Power RISC Core

elf-parser

Lightweight elf binary parser with no external dependencies - Sections, Symbols, Relocations, Segments

firmware-anatomy

Tear the firmware apart with your bare hands;-)

fpga-acc

fpgavirusscanner

Program to scan for malicious FPGA designs.

high-level-synthesis-flow-on-zynq-using-vivado-hls

This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.

hisa

Hardware Isolation-based Secure Architecture for CPU-FPGA Embedded Systems

hp0_2dma_smmu_driver_demo

keystone

Keystone Enclave (QEMU + HiFive Unleashed)

keystone-demo

Demo host and enclave applications exercising most functionality.

nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

opentitan

OpenTitan: Open source silicon root of trust

optee_client

Normal World Client side of the TEE

optee_examples

OP-TEE Sample Applications

optee_test

Test suite

pynq_cnn_accelerator_tutorial

中文：

rbos

使用Linux Security Module 为linux内核添加基于角色的访问控制功能

rocket-chip

Rocket Chip Generator

sgxfail

SGX从入门到放弃

shadowsocksx-ng-r8-bakup

Backup for ShadowsocksX-NG-R8.

shef

Shielded Enclaves for Cloud FPGAs

siphash

Hardware implementation of the SipHash short-inout PRF

ss-and-ssr-collection

常用资源汇集，仅个人收集向

static-5-pipeline-cpu

Computer Architect(B62008H) HW, verilog, MIPS

tee-hardware

TEE hardware - based on the chipyard repository - hardware to accelerate TEE

timberv-riscv-tools

RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)