How can the Rocket example provided by Difftest support extended instructions? about difftest HOT 8 CLOSED

B extension does not require special handling in DiffTest, since B extension uses the same general-purpose registers as the RV64GC.

Difftest requires extra bundles defined for F/D, Vector (DiffArchVecRegState, DiffVecCSRState) and Hypervisor (DiffHCSRState) extensions.

Therefore, not supporting B extension should not be related to difftest.

If you find rocket not support B ext, please refer to rocket readme/help for how to enable this extension.

If you find the simulation framework unable to test B extensions, it's most likely you are not using a reference model (NEMU/Spike) with B extension enabled. You may refer to their readme to see how to enable B extension.

from difftest.

Thank you for your prompt response.

I followed your suggestions and made modifications to both Rocket and Spike, and it worked for the B ext ! 😊

However, could you provide more information or approaches on how to support the V extension?

Thanks!

from difftest.

Never mind, it seems that Xiangshan is a good example to learn how to support other extensions. You can close this issue whenever you like.

Thank you.

from difftest.

After the changes, the log output at the top shows:

The first instruction of core 0 has commited. Difftest enabled. 
No instruction of core 0 commits for 500 cycles, maybe get stuck
(please also check whether a fence.i instruction requires more than 500 cycles to flush the icache)
Let REF run one more instruction.
...
> The normal instruction flow is displayed below.

May I ask if this prompt can be ignored?

from difftest.

However, could you provide more information or approaches on how to support the V extension?

Besides XiangShan, which is a good start point, I would recommend just reading the Difftest.scala. You can infer from the Bundle definitions that only DiffArchVecRegState, DiffVecCSRState are for vector (also can be seen from the commit 4ec40ea). Thus, the only thing to do is instantiting the corresponding DifftestModule in the design-under-test the same way as other bundles. I believe it would be easy for you to add these bundles in your own design.

from difftest.

After the changes, the log output at the top shows:

The first instruction of core 0 has commited. Difftest enabled. 
No instruction of core 0 commits for 500 cycles, maybe get stuck
(please also check whether a fence.i instruction requires more than 500 cycles to flush the icache)
Let REF run one more instruction.
...
> The normal instruction flow is displayed below.

May I ask if this prompt can be ignored?

It means the design-under-test may be stucked (no commits for 500 cycles) at executing some instruction.

While this cannot be ignored, this suggests something wrong with the design-under-test or how you connect them. DiffInstrCommit does not receive any commit in the last 500 cycles.

If the design does take more than 500 cycles to execute, you may need to enlarge this limit in difftest.h.

However, the more likely reason is, just as it says, the design-under-test may be stucked at some instruction. You can see from the logs displayed for the last instruction executed (marked as <-). You can check the design-under-test why this instruction does not commit in the last 500 cycles.

from difftest.

Never mind, it seems that Xiangshan is a good example to learn how to support other extensions. You can close this issue whenever you like.

I'm closing this issue to indicate the completion. However, you can still reply to this issue to track future problems.

If you encounter another problem, please feel free to raise a new issue with the corresponding title for the new problem.

from difftest.

Thank you for your detailed explanation and kind reminder!

from difftest.