jpwang's Projects
ABC: System for Sequential Logic Synthesis and Formal Verification
Circuit IR Compilers and Tools
NJU Compiler Lab
The CompCert formally-verified C compiler
常用英语词汇表
ics-wiki
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
NJU irsim in rust
an implementation of sparse matrix using linked list
Nash Equilibria Solver using python
Beamer sample for NJUer!
GitHub Profile
blog
A parser generator written in C++
A 2048 game mini Project with QT
Python-based Hardware Design Processing Toolkit for Verilog HDL
简单的正则表达式识别器
The ray tracing in one weekend series programs written in rust
simple Select And Translate tool for linux
NJU SE lab
SystemVerilog compiler and language services
CS144 Lab Assignments
SystemVerilog linter
An easy-to-learn/use static analysis framework for Java
Implement type checkers from Types and Programming Languages using haskell
NJU FLA Project
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Verilator open-source SystemVerilog simulator and lint system
XLS: Accelerated HW Synthesis