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Hi there 👋

  • 👋 I'm @olahiuj
  • 🔭 Recently working on building interpreters and type checkers
  • 🌱 Currently learning Haskell and Type Systems
  • 💬 Ask me about ...
  • 📫 How to reach me: [email protected]

jpwang's Projects

abc icon abc

ABC: System for Sequential Logic Synthesis and Formal Verification

circt icon circt

Circuit IR Compilers and Tools

compcert icon compcert

The CompCert formally-verified C compiler

llvm-project icon llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

mymatrix icon mymatrix

an implementation of sparse matrix using linked list

parsir icon parsir

A parser generator written in C++

pyverilog icon pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

re icon re

简单的正则表达式识别器

rtus icon rtus

The ray tracing in one weekend series programs written in rust

sator icon sator

simple Select And Translate tool for linux

slang icon slang

SystemVerilog compiler and language services

tai-e icon tai-e

An easy-to-learn/use static analysis framework for Java

tapl-hs icon tapl-hs

Implement type checkers from Types and Programming Languages using haskell

verible icon verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

verilator icon verilator

Verilator open-source SystemVerilog simulator and lint system

xls icon xls

XLS: Accelerated HW Synthesis

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