odahaoui Goto Github PK

8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

adas_project-auto-steering-acc

This is the final project of EECS 461 in University of Michigan. The goal of the project is to simulate Auto steering and Adaptive Cruise Control.

can-bus-communication-between-two-pic18f25k80

CAN BUS Communication between two PIC18F25K80 using MCP2551

core_uriscv

Another tiny RISC-V implementation

fft_fir_filter

FFT-based FIR Filter

fp_adder

Floating Point Adder in VHDL and Verification of result with matlab code

iir-audio-filter-fpga

Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA

mips

A pipelined MIPS processor written in VHDL (Unicamp/MC542)

pipeline-mips-verilog

A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

plong

Simple pong implementation in vhdl

riscv

A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning

rpu

Basic RISC-V CPU implementation in VHDL.

simple-9-bits-processor

A Simple 9 bits Processor implemented on a DE1 SOC.

simplecache

Simple cache design implementation in verilog

weathery