ariane

Ariane is a 6-stage RISC-V CPU

axi4_lite_interface

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

bank_managment_system

This is c++ repository which is based on implementation of oops topics like single , multiple and multilevel inheritance

football_management_system

Football management system DBMS python GUI project repository . This project is design on mysql database with python tiknter library for making a gui for the user

fpgas

muhammadtalhasami

My GitHub Profile README. Don't just fork, star it ⭐, so others can find it too! 🤝. Contributors are welcome.Feel free to contribute on my readme to make it more awesome 🔥🔥

oops

Oops object oriented programming language.This repo is basically a learning journey that how you implements the oops concepts in c++

openlane

This is my openlane repository in which we perform synthesis of our design/module.

rtl_practice

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

rv32i_processor_sv

In this repo you will get the step by step implementation of Rv32i processor from the Basic instructions to the 5-stage pipeline.Tool used for this are verilator and Vivado

rv32i_single_cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

rv32i_single_cycle_logisim

An implementation of rv32i single cycle processor on logisim

snk

🟩⬜ Generates a snake game from a github user contributions graph and output a screen capture as animated svg or gif

sv_verilator

System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .

verilog_practice

Verilog is a hardware description language. This repo is basically a learning journey of verilog