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Comments (3)

JimmyStones avatar JimmyStones commented on August 31, 2024

@sorgelig This was identified in the old Arcade-SnapJack core but never reported, but we've now confirmed it happens in the new merged core as well so I asked @thepulserifle to report it here with evidence

from arcade-ladybug_mister.

paulb-nl avatar paulb-nl commented on August 31, 2024

This is something that rarely happens for me but I was able to find the issue.

Gating the Char & Color RAMs access here with clk_en_4mhz_i causes much too short data output.

if clk_en_4mhz_i = '1' and -- operate RAMs with CPU clock

Please try the below core and see if it is fixed:
Arcade-LadyBug_20240602.zip

from arcade-ladybug_mister.

paulb-nl avatar paulb-nl commented on August 31, 2024

I found that the Wait signal for the CPU is sometimes cleared too early.

The b1_ff signal is supposed to delay the Wait clear when a new scroll value is loaded in at the falling edge of hx_ctrl_q.

wait_clear_q <= wait_q and (h_ctrl_s(3) and (b1_ff_q or hx_ctrl_q));

b1_ff should go high at the falling edge of h_ctrl_s(3) which is done here:
elsif h_ctrl_n_rise_s(3) = '1' then
-- rising edge indicator acts as clock enable instead of clock
b1_ff_s <= '1';
end if;

The problem is that h_ctrl_n_rise_s is wrong and b1_ff goes high at the rising edge of h_ctrl_s(3).

h_ctrl_n_rise_s <= h_ctrl_s and not h_ctrl_d_n_out_s;

It should be

h_ctrl_n_rise_s <= h_ctrl_s and not h_ctrl_d_out_s;

Here is a new core with the fix:
Arcade-LadyBug_20240606.zip

from arcade-ladybug_mister.

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