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Hello kkdas088, in FPGAs, the PLL (which generates the needed clock signals) is a vendor-specific component. For instance, for Altera/Intel FPGAs, a "altpll" needs to be instantiated (the "alt" in "altpll" standing, of course, for Altera).
If you're trying to synthesize for, e.g., a Xilinx device, the synthesizer will not be able to find "altpll". Instead you'll need to create you own code to instantiate properly configured PLLs. This can be done using the configuration options (a "wizard" - which is why "my" PLLs are named "wizpll" and "wizpll_vga") in the respective development environments.
In the basic setup, "wizpll" just generates a 50 MHz clock signal, while "wizpll_vga" generates a 25 MHz clock. Those should be easy to replace with whatever PLL configuration you can generate for you FPGA board.
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Thanks for the quick response. I was able to synthesize Tomthumb on Xilinx Virtex FPGA, by using their PLL, as advised by you. Thanks again
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