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bdf

Avnet Board Definition Files

blackman_harris_win

Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator)

blake2

Hardware implementation of the blake2 hash function

blake2-1

VHDL implementation of BLAKE2 cryptographic hash and message authentication code (MAC)

cbindgen

A project for generating C bindings from Rust code

csi2_rx

MIPI CSI-2 RX

data-encryption-standard-verilog

Data Encryption Standard- Verilog

demo_project

dma_ip_drivers

Xilinx QDMA IP Drivers

dspfilters

A collection of demonstration digital filters

edge-ai-platform-tutorials

Tutorials for the Edge AI Platform

fastai

The fastai deep learning library, plus lessons and and tutorials

fp23fftk

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

fpga-drive-aximm-pcie

Example designs for FPGA Drive FMC

fpga-hash-table

Simple hash table on Verilog (SystemVerilog)

go-filecoin

Filecoin Full Node Implementation in Go

h.265_encoder

haddoc2

Caffe to VHDL - by DREAM research group

hdl

hw

RTL, Cmodel, and testbench for NVDLA

linux-xlnx

The official Linux kernel from Xilinx

md5

MD5 in VHDL

openh264

Open Source H.264 Codec

openisp

Image Signal Processor

poseidon252

rosetta

Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

rtl_map

FFT-based visualizer for RTL-SDR devices. (RTL2832/DVB-T)

sha-256

An SHA-256 module implementation in VHDL. Based on NIST FIPS 180-4.

sha256

A simple SHA-256 implementation in VHDL

sha256_verilog

Verilog based FPGA Design of SHA256 Simulated on ModelSim