Comments (6)
Quartus によるテストテンプレートの自動生成
http://www.altima.jp/column/fpga_edison/testbench.html
便利そうだけど、チェックは人の手でやることに変わりはない
http://www.cqpub.co.jp/hanbai/books/MDD/MDDZ201010/DDT.pdf
http://www.cqpub.co.jp/dwm/contents/0130/dwm013001260.pdf
テストベンチの結果を用意したレジスタに読み込んで、比較器でチェックする方法だけど、テストケースが増えれば増えるほど辛そう
from computer-architecture-3s.
VUnit
https://github.com/VUnit/vunit
https://vunit.github.io/
System Verilog のため使えない
from computer-architecture-3s.
SVUnit
https://github.com/nosnhojn/svunit-code/
https://www.linkedin.com/pulse/svunit-real-verilog-test-framework-neil-johnson
System Verilog のため使えない
from computer-architecture-3s.
Cocotb
https://github.com/potentialventures/cocotb
CLI でできる。
ModelSim に対応
Verilog に対応
良さそう。
from computer-architecture-3s.
WIP cocotbのインストール
vagrant ssh
# URL: http://cocotb.readthedocs.io/en/latest/quickstart.html
# URL: https://github.com/potentialventures/cocotb/issues/396
$ sudo apt-get install -y build-essential swig python-dev libx32gcc1 gcc-multilib libstdc++-5-dev:i386 g++-multilib lib32z1 lib32stdc++6 lib32gcc1 expat:i386 fontconfig:i386 libfreetype6:i386 libexpat1:i386 libc6:i386 libgtk-3-0:i386 libcanberra0:i386 libpng12-0:i386 libice6:i386 libsm6:i386 libncurses5:i386 zlib1g:i386 libx11-6:i386 libxau6:i386 libxdmcp6:i386 libxext6:i386 libxft2:i386 libxrender1:i386 libxt6:i386 libxtst6:i386
# Install Python 2.7.9 on 32bit arch
$ wget https://www.python.org/ftp/python/2.7.9/Python-2.7.9.tgz
$ tar xvf Python-2.7.9.tgz
$ cd Python-2.7.9
$ echo "export PY32_DIR=/opt/pym32" >> ~/.bash_profile && source ~/.bash_profile
$ ./configure CC="gcc -m32" LDFLAGS="-L/lib32 -L/usr/lib32 -Lpwd/lib32 -Wl,-rpath,/lib32 -Wl,-rpath,$PY32_DIR/lib" --prefix=$PY32_DIR --enable-shared
$ make
$ sudo make install
$ cd ~ && git clone https://github.com/potentialventures/cocotb.git
$ echo 'export PATH="$HOME/intelFPGA_lite/18.0/modelsim_ase/linuxaloem:$PATH"' >> ~/.bash_profile
テストの実行
ARCH=i686 SIM=modelsim make
from computer-architecture-3s.
テストは、自前のアセンブラコードで行った。
from computer-architecture-3s.
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