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Kavin Raj Dennis

Digital Design Engineer @ Texas Instruments

Profile

Contact

Mail : [email protected]

Intrested In

  • Computer Architecture
  • RISC V
  • SoC Design

Skills

  • Digital circuit Design, RTL Design
  • System Verilog, Verilog
  • Synthesis, Equivalence Checking
  • Basics of UPF and SDC
  • Low Power Design
  • Static Timing Analysis
  • RTL-to-GDS flow
  • Perl / Python / Tcl Scripting
  • Bash/Csh Linux Shell
  • Finite State Machine Design
  • Computer Architecture
  • Computer Hardware

EDA Tool Experience

  • Simulation
    • vcs
    • xcelium
  • Synthesis
    • fusion compiler
    • genus
  • Static Checks ( Lint | CDC )
    • spyglass
    • jaspergold
  • Equivalence Checking
    • conformal
  • Physical Design
    • innovus
    • virtuoso
  • Timing
    • tempus
  • General
    • git
    • vim

Kavin Raj D's Projects

Kavin Raj D doesnโ€™t have any public repositories yet.

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