justinbalexander / zig-cortex Goto Github PK

This first milestone will be to reproduce at least the same subset of functionality as CMSIS.

While the functionality will be the same, this will not be a translation of CMSIS but rather a fresh rewrite in Zig with a (hopefully) improved and expressive API.

Every function or register definition must be documented with the document number combined with the section and/or table where the information was found for cross-referencing purposes.

For example:

/// ARM DDI 0403E.b Section B3.2
/// Table B3-3
const SCS_BASE = 0xE000E000;
const SYSTICK_BASE = SCS_BASE + 0x010;
const NVIC_BASE = SCS_BASE + 0x100;
const SCB_BASE = SCS_BASE + 0xD00;
const MPU_BASE = SCS_BASE + 0xD90;
const SCS_DEBUG_BASE = SCS_BASE + 0xDF0;
const CACHE_MAINTENANCE_BASE = SCS_BASE + 0xF50;
const MCU_ID_BASE = SCS_BASE + 0xFD0;

The document number including the version is there.

The resulting function and/or register definition should match the architecture reference manual from which it was pulled. CMSIS changed some register names and this rewrite should follow the reference manuals exactly. If there is a deviation from this convention, it must be documented and justified in a comment.

A list of functionality that must be matched will be checked off here:

• Register Addresses
• Interrupts: enable/disable, priority masks
• Get special registers/ status registers
• Core instructions that require assembly (NOP, WFE, etc)
• Config file to select architecture
• Data and instruction cache control
• Memory Protection Unit
• "SysTick" aka Periodic Interval Timer
• Clock frequency?
• Tightly Coupled Memory

Further functionality will be filed as separate issues.