jerry-d Goto Github PK
Name: Jerry D. Harthcock
Type: User
Location: Austin, Texas
Jerry D. Harthcock's Projects
64-bit-universal-floating-point-isa-compute-engine
RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
conscious_gate_transistor
Conscious Gate Transistor for creating conscious computers and machines. Provisional Patent Application with OpenSCAD 3D models.
customasm-for-sympl-isa
SYMPL ISA Rule table for open-source CustomASM cross-assembler.
hedgehog-fused-spiking-neural-network-emulator-compute-engine
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
ieee-754-2008-emulator
Universal IEEE 754-2008 Floating-Point Emulator for Xilinx and Altera FPGAs. Implements in hardware the entire (required) repertoire for half, single and double-precision binary formats, but with range limited to 5 bits and precision to 10 bits. If you require greater range and precision, contact me.
ieee-754-2008-fused-multiply-add
Fully pipelined IEEE 754-2008 "universal" Fused Multiply-Add operator in Verilog RTL directly accepts H=20 decimalCharacterSequence, binary16, binary32 and binary64 formatted numbers as operands.
ieee-754-2008-h-20-convertfromdecimalcharacter
Fully pipelined IEEE 754-2008 H=20 "convertFromDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAs
ieee-754-2008-h-20-converttodecimalcharacter
Fully pipelined IEEE 754-2008 H=20 "convertToDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAs
ieee-754-2008_isa_cpu
World's first and only 64-bit IEEE 754-2008 Instruction Set Architecture CPU implements "all" mandated operations in hardware with a single instruction per operation.
risc-v-sympl-hybrid-floating-point-isa-compute-engine
New hybrid ISA genetically splices the instruction pipeline of a RISC-V to the instruction pipelines of one or more SYMPL Compute Engines, giving you the best of both worlds in a single package.
sympl-gp-gpu-compute-engines
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
sympl_ieee754-2019_isa
SYMPL IEEE 754-2019 Instruction Set Architecture Compute Engine
tek4010
Free Tektronix 4010, 4013, 4014 and 4015 terminal emulator for Raspberry Pi and Ubuntu
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