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  • šŸ‘‹ Hi, Iā€™m @jaycordaro
  • šŸ‘€ Iā€™m interested in ... timing, jitter, FPGAs, electronics, and machine learning

Jay Cordaro's Projects

74auc-experiments icon 74auc-experiments

just a simple test board to test out JLC PCB's 4 layer boards and evaluate 74AUC logic

audio_gain icon audio_gain

SystemVerilog Audio gain block. Capable of adjusting PCM audio gain from -22dB to +22dB. SPI register interface

clkbrd3 icon clkbrd3

32kHz Low power crystal oscillator using 74AUP logic

half-band-filter icon half-band-filter

An implementation of an FIR half-band filter, from MATLAB floating point to SystemVerilog fixed point

i2s-toneplayer icon i2s-toneplayer

SystemVerilog I2S target, interfaces with an I2S controller. Controller sources WS and SCK

nomult_fir icon nomult_fir

lowpass FIR filter for Pulse Density Modulation (PDM) digital microphones that does not use multipliers

pdmbrd icon pdmbrd

Analog audio to Pulse Density Modulation (PDM) using OnSemi FAN3852 ICs

py_gpib icon py_gpib

Python GPIB Utilities using Prologix GPIB USB adapter

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