Board may not boot on all VGA monitors about amiga-2000-eatx HOT 8 CLOSED

Thanks for this information. I will look at this change for Rev 2.1.

from amiga-2000-eatx.

390682-01 schematic at the link below.

http://amigadev.elowar.com/read/ADCD_2.1/AmigaMail_Vol2_guide/node020B.html

from amiga-2000-eatx.

I altered the video output circuit to include the 74HCT08 buffer on both VSYNC and HSYNC. This requires adding an additional 74HCT08 (U207) and associated bypass cap (C207). Schematic attached. This is on Rev 2.1, which is intended to be the next production revision.

video-Video.pdf

from amiga-2000-eatx.

I looked at this more today and moved the HSYNC gate before J9004. COMPSYNC is already buffered by U205. It is not necessary to buffer it twice. Updated schematic attached.

video-Video.pdf

from amiga-2000-eatx.

A couple of observations/comments on this issue.

1. Where is U303C on the schematics? I cannot locate it on either 1.21 or 2.0. I suspect it should be listed as a spare as per originating issue. Are there any other unidentified spare logic gates that need to be flushed out?

2. Looking at the HSYNC vs VSYNC, I'm not sure I see why one is affected and not the other. HSYNC has a single TTL load difference as compared to VSYNC, which seems insignificant. None the less I agree buffering both is appropriate. However, NMOS ICs are not usually able to drive logical 1 very well. There is already a 10k (R203) pull up for HSYNC, but none for VSYNC. Perhaps coincidentally, HSYNC is asked to drive a TTL load where-as VSYNC is not. My suggestion to make this a bit more bullet proof would be to change R203 to 4.7k and add a 10k (or 4.7k) pullup to VSYNC to assist with TTL loads when H/V SYNC are logic 1.

3. Instead of adding a new logic chip to serve as a buffer, have you considered revisiting some of the existing logic to ensure efficient use? As an example, U607 stands out like a sore thumb as all ANDs are configured as a buffer. If geographically possible, I would suggest replacing U607 with a 74x34 hex buffer. Use four buffers in place of the current AND/Buffer gates, and the two extra buffers for HSYNC/VSYNC. This is just an example, but other opportunities may exist. Below are gates I found just casually looking that are masquerading as a buffer or inverter. There might be some I missed...

from amiga-2000-eatx.

1. Where is U303C on the schematics? I cannot locate it on either 1.21 or 2.0. I suspect it should be listed as a spare as per originating issue. Are there any other unidentified spare logic gates that need to be flushed out?

Spares are intended to be listed on the power sheet of the schematics. I missed U303C. Calling out spares wasn't a priority for the first round of the project. 8^>

2. Looking at the HSYNC vs VSYNC, I'm not sure I see why one is affected and not the other. HSYNC has a single TTL load difference as compared to VSYNC, which seems insignificant. None the less I agree buffering both is appropriate. However, NMOS ICs are not usually able to drive logical 1 very well. There is already a 10k (R203) pull up for HSYNC, but none for VSYNC. Perhaps coincidentally, HSYNC is asked to drive a TTL load where-as VSYNC is not. My suggestion to make this a bit more bullet proof would be to change R203 to 4.7k and add a 10k (or 4.7k) pullup to VSYNC to assist with TTL loads when H/V SYNC are logic 1.

Curious as to why the value change and difference in recommendation (4.7k vs 10k). As a side note, _VSYNC supplies the TICK signal to U300. This is related to CIA timing.

3. Instead of adding a new logic chip to serve as a buffer, have you considered revisiting some of the existing logic to ensure efficient use? As an example, U607 stands out like a sore thumb as all ANDs are configured as a buffer. If geographically possible, I would suggest replacing U607 with a 74x34 hex buffer. Use four buffers in place of the current AND/Buffer gates, and the two extra buffers for HSYNC/VSYNC. This is just an example, but other opportunities may exist. Below are gates I found just casually looking that are masquerading as a buffer or inverter. There might be some I missed...

I don't see anything like a 74x34. Maybe you meant a 74x367? That is a non-inverting hex buffer. Probably doable. The obvious candidate is U607. Its nearby and, as you point out, every gate is used as a buffer. I will take a look.

Most of the logic gates mentioned are geographically distant. Combining them would require a lot of work to re-route the board. Probably not worth it if the goal is to reduce part count by 1 or 2 cheap logic chips.

Add to the your list...
U303D is shown on the processor sheet and contributes to bus arbitration. Not a buffer.

from amiga-2000-eatx.

I don't see anything like a 74x34. Maybe you meant a 74x367?

I was being generic. 7436 is a hex buffer. Any buffer would work that is currently available. The AHCT244 already used would also be fine. These are octal rather than hex.

Most of the logic gates mentioned are geographically distant. Combining them would require a lot of work to re-route the board. Probably not worth it if the goal is to reduce part count by 1 or 2 cheap logic chips.

If it's too much effort then I agree - it was just a suggestion for you to think about, nothing more.

Add to the your list...U303D

Something got lost in translation, I think. U303D isn't on my list. As you note it's used as an AND gate.

Curious as to why the value change and difference in recommendation (4.7k vs 10k).

This will take some explaining but in retrospect I no longer believe any change is necessary. Disregard.

The explanation why I thought it was necessary (warning, long and rambling...):

The reason pullup resistors might be needed has to do with limitations of NMOS logic, where logic 1 outputs are inherently “weak”. This can be seen in the Denise (and other NMOS ICs) datasheet:

Characteristic      Symbol  Min  Max  units  Conditions
Output high level   Voh     2.4  -    volts  Ioh = -200ua
Output low level    Vol     -    0.4  volts  Iol = 3.2ma

Source: Datasheets/252126-01_Denise_specification.pdf para 3.3 in this repo

Note a logic 0 can sink up to 3.2mA, but a logic high can only source 200uA. If the application requires 200uA from the output, the voltage can drop to as low as 2.4V. The reason for this is because there is no easy way to push out current using only NMOS transistors. For the nerdy explanation, the NMOS NAND gate on Wikipedia provides a great illustration.

Source: https://en.wikipedia.org/wiki/Depletion-load_NMOS_logic

When both A and B are high, FETs T2 and T3 both turn on. This more or less directly connects the output Y to ground. This turns off T1 and produces a logic 0 at the Y output. Since Y is connected to ground through T2 and T3, it can handle a relatively high amount of current coming into the input.

Now consider if a logic 0 is applied to A or B (or both). T2 and/or T3 turn off, which causes Y to float. The voltage at Y increases only because some current leaks through T1. As the voltage increases, eventually it reaches a point where T1 barely turns on, producing a logic 1 at output Y. In real life this means the transition of NMOS outputs from low to high tends to be “lazy”. It also means that even a small load at Y will drop the output voltage, causing T1 to start to turn off, reducing the voltage at Y further.

This is not normally an issue when driving other NMOS logic, as the inputs are FETs which require very little power to drive. The input to bipolar logic (i.e. 74LSxxx) is however completely different and a high input can require more power than NMOS can deliver, especially when multiple inputs are driven at once. One solution to this problem is to use pullup resistors which “help” the NMOS output stage achieve a stable logic 1 output.

In this case, however, we are not driving bipolar logic, but HCT (CMOS) logic, which has a FET input stage likely similar to NMOS. Per the TI 74HCT08 datasheet, a high input only requires 1uA max (so a 2uA load per buffer, as configured). So, on paper, pullups are not necessary. Since the original A2000 Rev 6 schematic shows pullups on Denise outputs, but are unpopulated on A2000 boards (and don’t even exist on this project), it would seem to confirm the paper analysis. This is likely valid so long as (A)HCT buffers are used.

from amiga-2000-eatx.

Closing this issue -

I have duplicated the behavior described in the original post.
I have validated the proposed solution.
The solution is included in Rev 2.1, which will be the next production version.

Thanks, everyone!

from amiga-2000-eatx.