Comments (3)
Before thinking about a hardware support for the stack, I would implement a TRAN PC / REG and TRAN REG / PC. This would allow a software stack, with little changes to the current architecture. I think the multiplexer on the PC would need updating and accordingly there would be an instruction that could read from PC.
from excelcpu.
I hope I'm not mistaken, but I didn't see any hardware stack support in this ISA. You could use one of the GPRs to simulate a stack, however. But now we're talking ABI spec.
Without a TRAN PC, REG
/TRAN REG, PC
or JMP REG
instruction, I can't see a trivial workaround to this issue.
I suppose you could theoretically implement a RET
instruction as a JMP IMM
, but before executing that instruction, modify the destination. You'd have a somewhat weird looking epilogue, because self-modifying code sucks, but it should work.
from excelcpu.
I think jump with call not good for excel cpu. excel cpu is already slow, should optimize running code by inlining function instead of having redundant call ret. like shader for gpu do.
from excelcpu.
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