ianjiangict Goto Github PK
Name: Ian Jiang
Type: User
Location: Beijing
Ian Jiang's Projects
coding-explore
Various programs for exploring a special coding issue
coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
coremark-pro
Containing dozens of real-world and synthetic tests, CoreMark®-PRO (2015) is an industry-standard benchmark that measures the multi-processor performance of central processing units (CPU) and embedded microcrontrollers (MCU)
gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
gem5-slicing
Work space for slicing based on Gem5 and SimPoint.
instruction-test
Test tools for assembly instructions.
litmus-tests-riscv
RISC-V architecture concurrency model litmus tests
opensbi
RISC-V Open Source Supervisor Binary Interface
printf
Tiny, fast, non-dependent and fully loaded printf implementation for embedded systems. Extensive test suite passing.
qemu
Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv-openboot
Bootloader for RISC-V processors.
riscv-pk
RISC-V Proxy Kernel
simpoint3.2
This is simpoints 3.2 version, fixed with some errors
speckle
A wrapper for the SPEC CPU2006 benchmark suite.
spi-tools
Simple command line tools to help using Linux spidev devices
tiny-linux
Script and configuration for building tiny linux
u-boot
"Das U-Boot" Source Tree
uart-monitor
Monitor the UART data.
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