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System Verilog and Emulation. Written all the five channels.
The Ultra-Low Power RISC Core
RTL, Cmodel, and testbench for NVDLA
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System Verilog simulator and the Mentor Graphics Veloce hardware emulator.
Express DLA implementation for FPGA, revised based on NVDLA.
Random instruction generator for RISC-V processor verification
RISC-V Formal Verification Framework
GNU toolchain for RISC-V, including GCC
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
A declarative, efficient, and flexible JavaScript library for building user interfaces.
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.