Comments (2)
Hmm, I think it's important that the assembler doesn't choose any one rule based on order -- in the future it would allow for new optimizations.
Do you have an example of an instruction set where such a pair of instructions came up? Identical in function and mnemonic? It feels like whenever there's a pair like that, you could simplify it down to a single instruction without conflicts. Or maybe there's something I'm not anticipating.
from customasm.
68k assembly is a good example for an Instruction set that has a lot of different instructions doing the same exact thing.
various Arimethic/Logic Instructions have 2 operands, one of which is "hardwired" for the specific instruction, while the 2nd Operand can be choosen from a list of aviable addressing modes.
for example, ADD has 3 different basic instructions:
one where 1 operand is always a Data Register, one where 1 Operand is always an Address Register, and one where 1 Operand is always an Immediate Value.
but the available addressing modes also include Data/Address Registers, and Immediate Data.
take the first ADD Instruction for example, as its possible Addressing modes for the second Operand you can choose an Address Register or an Immediate Value (among other actual Memory accessing modes)
so it's immosible to know if ADD D0, #42
is a Data ADD using the Immediate Addressing Mode, or an Immediate ADD using the Data Register Addressing Mode, as both are equally valid in this case.
this kind of overlap is everywhere in the 68k.
obviously they thought of that and technically ADD is always uses Data Registers, ADDA always usesAddress Registers, and ADDI always uses Immediate Data, etc.
but pretty much any 68k Assembler will accept you just using "ADD" for everything and does the actual choosing of which instruction to use on it's own.
so i wanted to do the same in CustomASM as well.
Hmm, I think it's important that the assembler doesn't choose any one rule based on order -- in the future it would allow for new optimizations.
even if it's a fully optional commandline parameter or a #prioritze top/bottom/random
directive you throw into your CPU definition?
from customasm.
Related Issues (20)
- Allow outputting banks to different output files
- Support for 32bit and 64bit floats HOT 1
- "no match found for instruction" when mnemonic is less than 4 characters long (and has a subruledef directly next to it) HOT 4
- pattern matching error: whitespace and constants after mnemomics cause pattern matching rules to be broken HOT 2
- Improve error message HOT 1
- No match for instruction with negative numbers HOT 7
- Feature request: allow use of \x in multi byte character string functions HOT 2
- Allow Constants as Slice Sizes HOT 1
- Apparently unable to handle parameter without preceeding whitespace HOT 5
- Feature request: functions with variable numbers of arguments
- bank start/end/firstfree symbols
- Feature Request: Packed Instructions HOT 2
- Feature request: fill bank with custom value instead of zeros HOT 3
- Failure to match when a number is followed by a % HOT 3
- Allow aliases for token substitution HOT 8
- Is it possible to parse statements like .data or .asciz? HOT 3
- ruledef does not match when last character of nested ruledef follows it on 0.13.5 HOT 1
- Matched braces break recursive ruledefs on 0.13.6
- "unknown symbol" error when start of label matches start of ruledef HOT 3
- stop the leading blank fill of a Bank (with the Intel Hex output) HOT 1
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from customasm.