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Harvard Architecture, Circuits, and Compilers's Projects

aladdin icon aladdin

A pre-RTL, power-performance model for fixed-function accelerators

deeprecsys icon deeprecsys

http://vlsiarch.eecs.harvard.edu/research/recommendation/

edgebert icon edgebert

HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference

flexasr icon flexasr

FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks

gem5-aladdin icon gem5-aladdin

End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.

llvm-tracer icon llvm-tracer

An LLVM pass to profile dynamic LLVM IR instructions and runtime values

smaug icon smaug

SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin

smaug_docs icon smaug_docs

Documentation for SMAUG. Autogenerated, do not manually edit.

trireme icon trireme

Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration

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