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If compilation log shows

Info (332111): Found 5 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
Info (332111): 1.000 alt_xcvr_reconfig_wrapper:host_ep7_pcie_ep_xcvr_cfg|alt_xcvr_reconfig:alt_xcvr_reconfig_wrapper_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|alt_xcvr_arbiter:pif[3].pif_arb|grant[0]
Info (332111): 1.000 alt_xcvr_reconfig_wrapper:host_ep7_pcie_ep_xcvr_cfg|alt_xcvr_reconfig:alt_xcvr_reconfig_wrapper_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|alt_xcvr_arbiter:pif[6].pif_arb|grant[0]
Info (332111): 1.000 osc_50_b3b
Info (332111): 1.000 pcie_refclk_p
Info (332111): 1.000 sv_reconfig_pma_testbus_clk_0

Then the result sof will not boot.

Hi Han,

I ran make build.nfsume for benchmark/fwd and received the following error:

*** timing violation ***
Slack (VIOLATED) :        -0.397ns  (required time - arrival time)
  Source:                 tile_0_lFwdTest_mem_alloc_mallcRequestFifo/D_OUT_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by userclk2  {[email protected] [email protected] period=4.000ns})
  Destination:            tile_0_lFwdTest_mem_alloc_iommu_regall_cbram_bram/RAM_reg_0/DIADI[7]
                            (rising edge-triggered cell RAMB36E1 clocked by userclk2  {[email protected] [email protected] period=4.000ns})

make[1]: *** [bits] Error 245
make: *** [build.nfsume] Error 2

VLDram 313: write data to 00002b535c0009b0 with index 0060 = 0
VLDram 314: write data to 00002b535c0009b0 with index 0040 = 1
indxRam 314: write data to 00002b535c0a09d0 with index 010 = 00
Setram 314: write data to 00002b535c140ad0 with index 01 = 202
Vacram 314: write data to 00002b535c14acd0 with index 00 = 00000001
Idxram 314: write data to 00002b535c14b210 with index 01 = 00

VLDram should not write to 0x40 with 1. need clean up.

When using buildcache for quartus_sh, sometimes buildcache stucks at communciate()

Cleanup to integrate blueswitch

• rewrite Si570 controller.
• rewrite LED controller.
• rewrite Button Controller.
• rewrite switchbutton controller.
• hide clock domain crossing fifo in an instance.

Hi,

the new DDR3 test seems unable to compile, and generates the following error message:

Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/nfsume/verilog/mkPcieEndpointX7.v
BSV_BO [ /home/netfpga/gitHub/connectal/bsv/HostInterface.bsv]
make[1]: *** No rule to make target obj/Ddr3Controller.bo', needed byobj/Portal.bo'. Stop.
make: *** [build.nfsume] Error 2

Thanks

process stuck after altera_map.tcl is completed if the project was compiled and cached before.

Bad c_local value poisons the whole network..

Disable to avoid un-defined output, need to look into why.

Do not use 50MHz to generate PHY level clock.

Error: "/home/netfpga/gitHub/sonic-lite/p4/examples/paxos/HostChannel.bsv", line 65, column 42: (T0140)
Cannot access fields in this expression since its type Pipe::PipeOut' has not been imported. Perhaps an import statement is missing, e.g.,import
Pipe::;'
make[1]: ** [obj/HostChannel.bo] Error 1
make: *** [build.nfsume] Error 2

                AFTER IMPORTING "Pipe INTO "HostChannel.bsv":

Error: "/home/netfpga/gitHub/sonic-lite/p4/examples/paxos/HostChannel.bsv", line 66, column 42: (T0016)
Field get' is not in the typePipe::PipeOut' which was derived for this
expression.
make[1]: *** [obj/HostChannel.bo] Error 1
make: *** [build.nfsume] Error 2

so that user can use

git clone --recursive [email protected]:cambridgehackers/connectal.git

to pull both connectal and sonic-lite.

Hi Han,

Acceptor should change message type from Phase1A (0) to Phase1B (1) and Phase2A (2) to Phase2B (3).

Warning: "/home/hwang/dev/connectal/bsv/PcieEndpointS5.bsv", line 187, column 9: (G0043)
Multiple reset signals influence rule host_ep7_capture_deviceid'. This can lead to inconsistent, non-atomic results when not all of these signals are asserted. Method calls by reset: Reset 1 (single_reset.new_rst): host_ep7_pcie_ep_pcie.tl_cfg_add at "/home/hwang/dev/connectal/generated/altera/ALTERA_PCIE_WRAPPER.bsv", line 776, column 27, host_ep7_pcie_ep_pcie.tl_cfg_ctl at "/home/hwang/dev/connectal/generated/altera/ALTERA_PCIE_WRAPPER.bsv", line 777, column 27, Reset 2 (host_ep7_pcie_ep_corerst.gen_rst): host_ep7_deviceReg.write During elaboration of rulecapture_deviceid' at
"/home/hwang/dev/connectal/bsv/PcieEndpointS5.bsv", line 187, column 9.
During elaboration of ep7' at "/home/hwang/dev/connectal/bsv/PcieHost.bsv", line 227, column 31. During elaboration of_a' at "/home/hwang/dev/connectal/bsv/PcieHost.bsv",
line 273, column 19.
During elaboration of host' at "/home/hwang/dev/sonic-lite/vsim/../SonicSimTop.bsv", line 66, column 16. During elaboration ofmkSonicSimTop' at
"/home/hwang/dev/sonic-lite/vsim/../SonicSimTop.bsv", line 59, column 8.
Warning: "/home/hwang/dev/connectal/bsv/PcieEndpointS5.bsv", line 193, column 9: (G0043)
Multiple reset signals influence rule host_ep7_pertick3'. This can lead to inconsistent, non-atomic results when not all of these signals are asserted. Method calls by reset: Reset 1 (single_reset.new_rst): host_ep7_pcie_ep_pcie.dl_up_exit at "/home/hwang/dev/connectal/generated/altera/ALTERA_PCIE_WRAPPER.bsv", line 584, column 26, host_ep7_pcie_ep_pcie.hotrst_exit at "/home/hwang/dev/connectal/generated/altera/ALTERA_PCIE_WRAPPER.bsv", line 603, column 28, host_ep7_pcie_ep_pcie.l2_exit at "/home/hwang/dev/connectal/generated/altera/ALTERA_PCIE_WRAPPER.bsv", line 616, column 24, host_ep7_pcie_ep_pcie.ltssm_state at "/home/hwang/dev/connectal/generated/altera/ALTERA_PCIE_WRAPPER.bsv", line 630, column 27, Reset 2 (host_ep7_hip_rs_npor_sync_pld_clk.gen_rst): host_ep7_hip_rs_dlup_exit_r.write host_ep7_hip_rs_hotrst_exit_r.write host_ep7_hip_rs_l2_exit_r.write host_ep7_hip_rs_ltssm_r.write During elaboration of rulepertick3' at

Error: "/home/netfpga/gitHub/sonic-lite/dtp/examples/pktgen_forwarding/DtpPktGenTop.bsv", line 106, column 17: (T0081)
Wrong number of arguments in the use of the following function:
mkEthMac

The function expects 3 arguments but was used with 4 arguments.

Expected type:
function a__#(EthMac::EthMacIfc) f(Clock x1, Clock x2, Reset x3)

Inferred type:
function f__#(g__) f(b__ x1, c__ x2, d__ x3, e__ x4)

Error: "/home/netfpga/gitHub/sonic-lite/dtp/examples/pktgen_forwarding/DtpPktGenTop.bsv", line 161, column 4: (T0031)
The provisos for this expression could not be resolved because there are no
instances of the form:
Connectable::Connectable#(GetPut::Get#(EthMac::PacketDataT#(64)), Pipe::PipeIn#(EthMac::PacketDataT#(64)))
make[1]: *** [obj/DtpPktGenTop.bo] Error 1
make: *** [build.nfsume] Error 2

If directly reading registers work in C. then the IRQ generation must the issue.

Currently goes to stdout.