Comments (4)
https://github.com/fireice-uk/xmr-stak-cpu/blob/master/crypto/cryptonight_aesni.h
Nearly every function is a SSE2 mnemonic.
There is a huge amount of performance that can be unlocked by implementing the algorithm using AVX.
What makes you say that?
Is there a document describing the algorithm or perhaps a suite of tests ?
https://cryptonote.org/cns/cns008.txt
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On the one hand, AVX instructions use 256 bit registers, compared to the 128 bit ones of SSE; the instruction set is richer, so the same thing can be implemented in fewer instructions and there are more registers.
So I do believe that there is some extra performance that can be unlocked this way.
Perhaps not that huge, though, as the algorithm is designed to be limited by cache.
My assumption was correct, that compared to Prime95, the difference in power draw comes from under utilizing the SIMD ALUs. But that is, perhaps, mostly because the ALUs are waiting for data from cache.
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Three major problems:
- AES block size is 128 bit.
- Product of two 64 bit number is 128 bit.
- Switch between AVX and non-AVX instruction set is insanely long.
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I see. Thank you.
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